segment_scan_clock_24.syr

設計VHDL24小時的時鐘

Optimizing unit <segment_scan_clock_24> ...

Optimizing unit <DECODER> ...

Optimizing unit <COUNT_00_23> ...
Loading device for application Xst from file 'v200.nph' in environment C:/Xilinx.

Mapping all equations...
WARNING:Xst:637 - Naming conflict between signal BCD<1> of unit DECODER and signal DECODER_BCD<1> of unit segment_scan_clock_24 : renaming DECODER_BCD<1> to DECODER_BCD<1>1.
WARNING:Xst:637 - Naming conflict between signal BCD<2> of unit DECODER and signal DECODER_BCD<2> of unit segment_scan_clock_24 : renaming DECODER_BCD<2> to DECODER_BCD<2>1.
WARNING:Xst:637 - Naming conflict between signal BCD<0> of unit DECODER and signal DECODER_BCD<0> of unit segment_scan_clock_24 : renaming DECODER_BCD<0> to DECODER_BCD<0>1.
WARNING:Xst:637 - Naming conflict between signal BCD<3> of unit DECODER and signal DECODER_BCD<3> of unit segment_scan_clock_24 : renaming DECODER_BCD<3> to DECODER_BCD<3>1.
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block segment_scan_clock_24, actual ratio is 2.

=========================================================================
*                            Final Report                               *
=========================================================================
Final Results
RTL Top Level Output File Name     : segment_scan_clock_24.ngr
Top Level Output File Name         : segment_scan_clock_24
Output Format                      : NGC
Optimization Goal                  : Speed
Keep Hierarchy                     : NO

Design Statistics
# IOs                              : 16

Macro Statistics :
# Registers                        : 15
#      1-bit register              : 14
#      25-bit register             : 1
# Counters                         : 4
#      4-bit up counter            : 4
# Adders/Subtractors               : 3
#      25-bit adder                : 1
#      4-bit adder                 : 2

Cell Usage :
# BELS                             : 186
#      GND                         : 1
#      LUT1                        : 35
#      LUT2                        : 4
#      LUT2_L                      : 1
#      LUT3                        : 8
#      LUT3_D                      : 1
#      LUT4                        : 38
#      LUT4_D                      : 5
#      MUXCY                       : 46
#      VCC                         : 1
#      XORCY                       : 46
# FlipFlops/Latches                : 59
#      FDC                         : 26
#      FDCE                        : 8
#      FDCPE                       : 16
#      FDP                         : 5
#      LD                          : 4
# Clock Buffers                    : 1
#      BUFGP                       : 1
# IO Buffers                       : 15
#      IBUF                        : 1
#      OBUF                        : 14
=========================================================================

Device utilization summary:
---------------------------

Selected Device : 2s200pq208-5 

 Number of Slices:                      58  out of   2352     2%  
 Number of Slice Flip Flops:            59  out of   4704     1%  
 Number of 4 input LUTs:                92  out of   4704     1%  
 Number of bonded IOBs:                 15  out of    144    10%  
 Number of GCLKs:                        1  out of      4    25%  


=========================================================================
TIMING REPORT

NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
      FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
      GENERATED AFTER PLACE-and-ROUTE.

Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal                       | Clock buffer(FF name)  | Load  |
-----------------------------------+------------------------+-------+
_n0030(_n003088:O)                 | NONE(*)(DECODER_BCD_1) | 4     |
CLK                                | BUFGP                  | 25    |
TIME_BASE_DIVIDER_25:Q             | NONE                   | 24    |
TIME_BASE_DIVIDER_15:Q             | NONE                   | 6     |
-----------------------------------+------------------------+-------+
(*) This 1 clock signal(s) are generated by combinatorial logic,
and XST is not able to identify which are the primary clock signals.
Please use the CLOCK_SIGNAL constraint to specify the clock signal(s) generated by combinatorial logic.

Timing Summary:
---------------
Speed Grade: -5

   Minimum period: 9.527ns (Maximum Frequency: 104.965MHz)
   Minimum input arrival time before clock: No path found
   Maximum output required time after clock: 10.731ns
   Maximum combinational path delay: No path found

Timing Detail:
--------------
All values displayed in nanoseconds (ns)

-------------------------------------------------------------------------
Timing constraint: Default period analysis for Clock 'CLK'
Delay:               6.580ns (Levels of Logic = 2)
  Source:            TIME_BASE_DIVIDER_25 (FF)
  Destination:       TIME_BASE_DIVIDER_25 (FF)
  Source Clock:      CLK rising
  Destination Clock: CLK rising

  Data Path: TIME_BASE_DIVIDER_25 to TIME_BASE_DIVIDER_25
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDC:C->Q             26   1.292   3.500  TIME_BASE_DIVIDER_25 (TIME_BASE_DIVIDER_25)
     LUT1:I0->O            0   0.653   0.000  CLOCK_rt (CLOCK_rt)
     XORCY:LI->O           1   0.382   0.000  TIME_BASE_DIVIDER_Madd__n0000_inst_sum_24 (TIME_BASE_DIVIDER__n0000<24>)
     FDC:D                     0.753          TIME_BASE_DIVIDER_25
    ----------------------------------------
    Total                      6.580ns (3.080ns logic, 3.500ns route)
                                       (46.8% logic, 53.2% route)

-------------------------------------------------------------------------
Timing constraint: Default period analysis for Clock 'TIME_BASE_DIVIDER_25:Q'
Delay:               9.527ns (Levels of Logic = 3)
  Source:            SECOND_COUNTER_COUNTER_1 (FF)
  Destination:       HOUR_TIME_BCD_4 (FF)
  Source Clock:      TIME_BASE_DIVIDER_25:Q rising
  Destination Clock: TIME_BASE_DIVIDER_25:Q rising

  Data Path: SECOND_COUNTER_COUNTER_1 to HOUR_TIME_BCD_4
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDCPE:C->Q            5   1.292   1.740  SECOND_COUNTER_COUNTER_1 (SECOND_COUNTER_COUNTER_1)
     LUT4_D:I1->O          7   0.653   1.950  SECOND_COUNTER__n00011 (SECOND_COUNTER_NINE)
     LUT3_D:I2->LO         1   0.653   0.100  MINUTE_COUNTER_CARRY1 (N5880)
     LUT3:I2->O            4   0.653   1.600  HOUR__n00151 (HOUR__n0015)
     FDCE:CE                   0.886          HOUR_TIME_BCD_6
    ----------------------------------------
    Total                      9.527ns (4.137ns logic, 5.390ns route)
                                       (43.4% logic, 56.6% route)

-------------------------------------------------------------------------
Timing constraint: Default period analysis for Clock 'TIME_BASE_DIVIDER_15:Q'
Delay:               3.995ns (Levels of Logic = 0)
  Source:            POSITION_4 (FF)
  Destination:       POSITION_5 (FF)
  Source Clock:      TIME_BASE_DIVIDER_15:Q rising
  Destination Clock: TIME_BASE_DIVIDER_15:Q rising

  Data Path: POSITION_4 to POSITION_5
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDP:C->Q              7   1.292   1.950  POSITION_4 (POSITION_4)
     FDP:D                     0.753          POSITION_5
    ----------------------------------------
    Total                      3.995ns (2.045ns logic, 1.950ns route)
                                       (51.2% logic, 48.8% route)

-------------------------------------------------------------------------
Timing constraint: Default OFFSET OUT AFTER for Clock 'TIME_BASE_DIVIDER_15:Q'
Offset:              8.799ns (Levels of Logic = 1)
  Source:            POSITION_5 (FF)
  Destination:       ENABLE<6> (PAD)
  Source Clock:      TIME_BASE_DIVIDER_15:Q rising

  Data Path: POSITION_5 to ENABLE<6>
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDP:C->Q              7   1.292   1.950  POSITION_5 (POSITION_5)
     OBUF:I->O                 5.557          ENABLE_6_OBUF (ENABLE<6>)
    ----------------------------------------
    Total                      8.799ns (6.849ns logic, 1.950ns route)
                                       (77.8% logic, 22.2% route)

-------------------------------------------------------------------------
Timing constraint: Default OFFSET OUT AFTER for Clock '_n003088:O'
Offset:              10.731ns (Levels of Logic = 2)
  Source:            DECODER_BCD_3 (LATCH)
  Destination:       SEGMENT<7> (PAD)
  Source Clock:      _n003088:O falling

  Data Path: DECODER_BCD_3 to SEGMENT<7>
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     LD:G->Q               7   1.421   1.950  DECODER_BCD_3 (DECODER_BCD_3)
     LUT4:I3->O            1   0.653   1.150  DECODER_SEGMENT<2>1 (SEGMENT_2_OBUF)
     OBUF:I->O                 5.557          SEGMENT_2_OBUF (SEGMENT<2>)
    ----------------------------------------
    Total                     10.731ns (7.631ns logic, 3.100ns route)
                                       (71.1% logic, 28.9% route)

-------------------------------------------------------------------------
Timing constraint: Default OFFSET OUT AFTER for Clock 'CLK'
Offset:              10.349ns (Levels of Logic = 1)
  Source:            TIME_BASE_DIVIDER_25 (FF)
  Destination:       SEGMENT<0> (PAD)
  Source Clock:      CLK rising

  Data Path: TIME_BASE_DIVIDER_25 to SEGMENT<0>
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDC:C->Q             26   1.292   3.500  TIME_BASE_DIVIDER_25 (TIME_BASE_DIVIDER_25)
     OBUF:I->O                 5.557          SEGMENT_0_OBUF (SEGMENT<0>)
    ----------------------------------------
    Total                     10.349ns (6.849ns logic, 3.500ns route)
                                       (66.2% logic, 33.8% route)

=========================================================================
CPU : 4.67 / 5.60 s | Elapsed : 5.00 / 6.00 s
 
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Total memory usage is 62188 kilobytes