segment_scan_clock_24.syr

設計VHDL24小時的時鐘

Release 6.1i - xst G.23
Copyright (c) 1995-2003 Xilinx, Inc.  All rights reserved.
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--> Reading design: segment_scan_clock_24.prj

TABLE OF CONTENTS
  1) Synthesis Options Summary
  2) HDL Compilation
  3) HDL Analysis
  4) HDL Synthesis
     4.1) HDL Synthesis Report
  5) Advanced HDL Synthesis
  6) Low Level Synthesis
  7) Final Report
     7.1) Device utilization summary
     7.2) TIMING REPORT


=========================================================================
*                      Synthesis Options Summary                        *
=========================================================================
---- Source Parameters
Input File Name                    : segment_scan_clock_24.prj
Input Format                       : mixed
Ignore Synthesis Constraint File   : NO
Verilog Include Directory          : 

---- Target Parameters
Output File Name                   : segment_scan_clock_24
Output Format                      : NGC
Target Device                      : xc2s200-5-pq208

---- Source Options
Top Module Name                    : segment_scan_clock_24
Automatic FSM Extraction           : YES
FSM Encoding Algorithm             : Auto
FSM Style                          : lut
RAM Extraction                     : Yes
RAM Style                          : Auto
ROM Extraction                     : Yes
ROM Style                          : Auto
Mux Extraction                     : YES
Mux Style                          : Auto
Decoder Extraction                 : YES
Priority Encoder Extraction        : YES
Shift Register Extraction          : YES
Logical Shifter Extraction         : YES
XOR Collapsing                     : YES
Resource Sharing                   : YES
Multiplier Style                   : lut
Automatic Register Balancing       : No

---- Target Options
Add IO Buffers                     : YES
Global Maximum Fanout              : 100
Add Generic Clock Buffer(BUFG)     : 4
Register Duplication               : YES
Equivalent register Removal        : YES
Slice Packing                      : YES
Pack IO Registers into IOBs        : auto

---- General Options
Optimization Goal                  : Speed
Optimization Effort                : 1
Keep Hierarchy                     : NO
Global Optimization                : AllClockNets
RTL Output                         : Yes
Write Timing Constraints           : NO
Hierarchy Separator                : _
Bus Delimiter                      : <>
Case Specifier                     : maintain
Slice Utilization Ratio            : 100
Slice Utilization Ratio Delta      : 5

---- Other Options
lso                                : segment_scan_clock_24.lso
Read Cores                         : YES
cross_clock_analysis               : NO
verilog2001                        : YES
Optimize Instantiated Primitives   : NO

=========================================================================

WARNING:Xst:1885 - LSO file is empty, default list of libraries is used

=========================================================================
*                          HDL Compilation                              *
=========================================================================
WARNING:HDLParsers:3215 - Unit work/SEGMENT_SCAN_CLOCK_24 is now defined in a different file: was C:/BOOK_ISE/SEGMENT_SCAN_CLOCK_24/SEGMENT_SCAN_CLOCK_24.VHD, now is C:/DMATEK_BOOK/SEGMENT_SCAN_CLOCK_24/SEGMENT_SCAN_CLOCK_24.VHD
WARNING:HDLParsers:3215 - Unit work/SEGMENT_SCAN_CLOCK_24/BEHAVIORAL is now defined in a different file: was C:/BOOK_ISE/SEGMENT_SCAN_CLOCK_24/SEGMENT_SCAN_CLOCK_24.VHD, now is C:/DMATEK_BOOK/SEGMENT_SCAN_CLOCK_24/SEGMENT_SCAN_CLOCK_24.VHD
WARNING:HDLParsers:3215 - Unit work/DECODER is now defined in a different file: was C:/BOOK_ISE/SEGMENT_SCAN_CLOCK_24/DECODER.vhd, now is C:/DMATEK_BOOK/SEGMENT_SCAN_CLOCK_24/DECODER.vhd
WARNING:HDLParsers:3215 - Unit work/DECODER/BEHAVIORAL is now defined in a different file: was C:/BOOK_ISE/SEGMENT_SCAN_CLOCK_24/DECODER.vhd, now is C:/DMATEK_BOOK/SEGMENT_SCAN_CLOCK_24/DECODER.vhd
WARNING:HDLParsers:3215 - Unit work/COUNT_00_23 is now defined in a different file: was C:/BOOK_ISE/SEGMENT_SCAN_CLOCK_24/COUNT_00_23.VHD, now is C:/DMATEK_BOOK/SEGMENT_SCAN_CLOCK_24/COUNT_00_23.VHD
WARNING:HDLParsers:3215 - Unit work/COUNT_00_23/BEHAVIORAL is now defined in a different file: was C:/BOOK_ISE/SEGMENT_SCAN_CLOCK_24/COUNT_00_23.VHD, now is C:/DMATEK_BOOK/SEGMENT_SCAN_CLOCK_24/COUNT_00_23.VHD
WARNING:HDLParsers:3215 - Unit work/COUNT_00_59 is now defined in a different file: was C:/BOOK_ISE/SEGMENT_SCAN_CLOCK_24/COUNT_00_59.VHD, now is C:/DMATEK_BOOK/SEGMENT_SCAN_CLOCK_24/COUNT_00_59.VHD
WARNING:HDLParsers:3215 - Unit work/COUNT_00_59/BEHAVIORAL is now defined in a different file: was C:/BOOK_ISE/SEGMENT_SCAN_CLOCK_24/COUNT_00_59.VHD, now is C:/DMATEK_BOOK/SEGMENT_SCAN_CLOCK_24/COUNT_00_59.VHD
WARNING:HDLParsers:3215 - Unit work/CLOCK_PACK is now defined in a different file: was C:/BOOK_ISE/SEGMENT_SCAN_CLOCK_24/CLOCK_PACK.vhd, now is C:/DMATEK_BOOK/SEGMENT_SCAN_CLOCK_24/CLOCK_PACK.vhd
WARNING:HDLParsers:3215 - Unit work/COUNT_0_5 is now defined in a different file: was C:/BOOK_ISE/SEGMENT_SCAN_CLOCK_24/COUNT_0_5.VHD, now is C:/DMATEK_BOOK/SEGMENT_SCAN_CLOCK_24/COUNT_0_5.VHD
WARNING:HDLParsers:3215 - Unit work/COUNT_0_5/BEHAVIORAL is now defined in a different file: was C:/BOOK_ISE/SEGMENT_SCAN_CLOCK_24/COUNT_0_5.VHD, now is C:/DMATEK_BOOK/SEGMENT_SCAN_CLOCK_24/COUNT_0_5.VHD
WARNING:HDLParsers:3215 - Unit work/COUNT_0_9 is now defined in a different file: was C:/BOOK_ISE/SEGMENT_SCAN_CLOCK_24/COUNT_0_9.VHD, now is C:/DMATEK_BOOK/SEGMENT_SCAN_CLOCK_24/COUNT_0_9.VHD
WARNING:HDLParsers:3215 - Unit work/COUNT_0_9/BEHAVIORAL is now defined in a different file: was C:/BOOK_ISE/SEGMENT_SCAN_CLOCK_24/COUNT_0_9.VHD, now is C:/DMATEK_BOOK/SEGMENT_SCAN_CLOCK_24/COUNT_0_9.VHD
WARNING:HDLParsers:3215 - Unit work/CLK_SET is now defined in a different file: was C:/BOOK_ISE/SEGMENT_SCAN_CLOCK_24/CLK_SET.VHD, now is C:/DMATEK_BOOK/SEGMENT_SCAN_CLOCK_24/CLK_SET.VHD
WARNING:HDLParsers:3215 - Unit work/CLK_SET/BEHAVIORAL is now defined in a different file: was C:/BOOK_ISE/SEGMENT_SCAN_CLOCK_24/CLK_SET.VHD, now is C:/DMATEK_BOOK/SEGMENT_SCAN_CLOCK_24/CLK_SET.VHD
Compiling vhdl file C:/DMATEK_BOOK/SEGMENT_SCAN_CLOCK_24/CLOCK_PACK.vhd in Library work.
Compiling vhdl file C:/DMATEK_BOOK/SEGMENT_SCAN_CLOCK_24/COUNT_0_9.VHD in Library work.
Entity <COUNT_0_9> (Architecture <Behavioral>) compiled.
Compiling vhdl file C:/DMATEK_BOOK/SEGMENT_SCAN_CLOCK_24/COUNT_0_5.VHD in Library work.
Entity <COUNT_0_5> (Architecture <Behavioral>) compiled.
Compiling vhdl file C:/DMATEK_BOOK/SEGMENT_SCAN_CLOCK_24/CLK_SET.VHD in Library work.
Entity <CLK_SET> (Architecture <Behavioral>) compiled.
Compiling vhdl file C:/DMATEK_BOOK/SEGMENT_SCAN_CLOCK_24/COUNT_00_59.VHD in Library work.
Entity <COUNT_00_59> (Architecture <Behavioral>) compiled.
Compiling vhdl file C:/DMATEK_BOOK/SEGMENT_SCAN_CLOCK_24/COUNT_00_23.VHD in Library work.
Entity <COUNT_00_23> (Architecture <Behavioral>) compiled.
Compiling vhdl file C:/DMATEK_BOOK/SEGMENT_SCAN_CLOCK_24/DECODER.vhd in Library work.
Entity <DECODER> (Architecture <Behavioral>) compiled.
Compiling vhdl file C:/DMATEK_BOOK/SEGMENT_SCAN_CLOCK_24/SEGMENT_SCAN_CLOCK_24.VHD in Library work.
Entity <SEGMENT_SCAN_CLOCK_24> (Architecture <Behavioral>) compiled.

=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing Entity <segment_scan_clock_24> (Architecture <Behavioral>).
Entity <segment_scan_clock_24> analyzed. Unit <segment_scan_clock_24> generated.

Analyzing Entity <CLK_SET> (Architecture <behavioral>).
Entity <CLK_SET> analyzed. Unit <CLK_SET> generated.

Analyzing Entity <COUNT_00_59> (Architecture <behavioral>).
Entity <COUNT_00_59> analyzed. Unit <COUNT_00_59> generated.

Analyzing Entity <COUNT_0_9> (Architecture <behavioral>).
Entity <COUNT_0_9> analyzed. Unit <COUNT_0_9> generated.

Analyzing Entity <COUNT_0_5> (Architecture <behavioral>).
Entity <COUNT_0_5> analyzed. Unit <COUNT_0_5> generated.

Analyzing Entity <COUNT_00_23> (Architecture <behavioral>).
Entity <COUNT_00_23> analyzed. Unit <COUNT_00_23> generated.

Analyzing Entity <DECODER> (Architecture <behavioral>).
Entity <DECODER> analyzed. Unit <DECODER> generated.


=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <COUNT_0_5>.
    Related source file is C:/DMATEK_BOOK/SEGMENT_SCAN_CLOCK_24/COUNT_0_5.VHD.
    Found 4-bit up counter for signal <COUNTER>.
    Summary:
	inferred   1 Counter(s).
Unit <COUNT_0_5> synthesized.


Synthesizing Unit <COUNT_0_9>.
    Related source file is C:/DMATEK_BOOK/SEGMENT_SCAN_CLOCK_24/COUNT_0_9.VHD.
    Found 4-bit up counter for signal <COUNTER>.
    Summary:
	inferred   1 Counter(s).
Unit <COUNT_0_9> synthesized.


Synthesizing Unit <DECODER>.
    Related source file is C:/DMATEK_BOOK/SEGMENT_SCAN_CLOCK_24/DECODER.vhd.
Unit <DECODER> synthesized.


Synthesizing Unit <COUNT_00_23>.
    Related source file is C:/DMATEK_BOOK/SEGMENT_SCAN_CLOCK_24/COUNT_00_23.VHD.
    Found 4-bit adder for signal <$n0000> created at line 32.
    Found 4-bit adder for signal <$n0001> created at line 34.
    Found 8-bit register for signal <TIME_BCD>.
    Summary:
	inferred   8 D-type flip-flop(s).
	inferred   2 Adder/Subtracter(s).
Unit <COUNT_00_23> synthesized.


Synthesizing Unit <COUNT_00_59>.
    Related source file is C:/DMATEK_BOOK/SEGMENT_SCAN_CLOCK_24/COUNT_00_59.VHD.
Unit <COUNT_00_59> synthesized.


Synthesizing Unit <CLK_SET>.
    Related source file is C:/DMATEK_BOOK/SEGMENT_SCAN_CLOCK_24/CLK_SET.VHD.
    Found 25-bit up counter for signal <DIVIDER>.
    Summary:
	inferred   1 Counter(s).
Unit <CLK_SET> synthesized.


Synthesizing Unit <segment_scan_clock_24>.
    Related source file is C:/DMATEK_BOOK/SEGMENT_SCAN_CLOCK_24/SEGMENT_SCAN_CLOCK_24.VHD.
WARNING:Xst:737 - Found 4-bit latch for signal <DECODER_BCD>.
    Found 6-bit register for signal <POSITION>.
Unit <segment_scan_clock_24> synthesized.


=========================================================================
HDL Synthesis Report

Macro Statistics
# Registers                        : 9
  1-bit register                   : 8
  6-bit register                   : 1
# Latches                          : 1
  4-bit latch                      : 1
# Counters                         : 5
  4-bit up counter                 : 4
  25-bit up counter                : 1
# Adders/Subtractors               : 2
  4-bit adder                      : 2

=========================================================================

=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================


=========================================================================
*                         Low Level Synthesis                           *
=========================================================================