decoder.vhd

設計VHDL24小時的時鐘

--**************************************
--*    BCD To Seven Segment Decoder    *
--*       Filename : DECODER.VHD	    *
--**************************************

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity DECODER is
    Port ( CLK     : in std_logic;
           BCD     : in std_logic_vector(3 downto 0);
           SEGMENT : out std_logic_vector(7 downto 0));
end DECODER;

architecture Behavioral of DECODER is

begin
  with BCD select
    SEGMENT <= "1000000" & CLK when "0000", 	--0
               "1111001" & CLK when "0001",	--1
               "0100100" & CLK when "0010",	--2
               "0110000" & CLK when "0011",	--3
               "0011001" & CLK when "0100",	--4
               "0010010" & CLK when "0101",	--5
               "0000010" & CLK when "0110",	--6
               "1111000" & CLK when "0111",	--7
               "0000000" & CLK when "1000",	--8
               "0010000" & CLK when "1001",	--9
   	          "1111111" & CLK when others;

end Behavioral;