shift_control.vhd

这是我做的I2C的vhdl程序和仿真和下载文件

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;

entity shift_control is
port(
  clk,
  iflag: in std_logic;
  dcnt:unsigned(3 downto 0);
  d:in std_logic_vector(7 downto 0);
  din:out std_logic
);
end shift_control;

architecture arc_shift_control of shift_control is

component p2s_altera is
port(
  clk,
  clkih, 
  stld,
  ser: in std_logic;

 d :in std_logic_vector(0 to 7);
 q,
 nq: out std_logic
);
end component p2s_altera;


--signal for p2s_altera
signal  iclkih,  istld, iser:std_logic;
signal do :std_logic;
signal flag: std_logic;

--signal for shift_control process
type shift_type is(s1,s2,s3);
signal shift_state: shift_type;

begin
shift: p2s_altera port map(clk,iclkih,istld,iser,d,din,do);

shift_control: process(clk,iflag,dcnt)
begin

  if(clk'event and clk='1') then
      case shift_state is
      when s1=>
             iclkih<='0';
             istld<='0';
             iser<='0';
             shift_state<=s2;
     when s2=>
             iclkih<='1';
             istld<='1';
             iser<='1'; 
             if iflag='1'   then 
                if(dcnt=8) then
                             shift_state<=s1;
                else 
                             shift_state<=s3;
                end if;
              else 
                           shift_state<=s2;
              end if;
        
    when s3=>
             iclkih<='0';
             istld<='1';
             iser<='1';   
             shift_state<=s2;  
    end case;
    end if;
end process shift_control;

end arc_shift_control;