📄 i2c_core.rpt
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# state~1 & !state~2 & state~4
# !state~1 & state~2 & state~5
# !state~1 & state~2 & state~4;
-- Node name is 'state~2~2'
-- Equation name is 'state~2~2', location is LC030, type is buried.
-- synthesized logic cell
_LC030 = LCELL( _EQ011 $ GND);
_EQ011 = !state~1 & state~2 & state~3
# state~1 & !state~2 & !state~3
# state~4 & state~5;
-- Node name is 'state~2'
-- Equation name is 'state~2', location is LC017, type is buried.
state~2 = DFFE( _EQ012 $ _EQ013, GLOBAL( clk), nreset, VCC, VCC);
_EQ012 = idcnt0 & !idcnt1 & !idcnt2 & !idcnt3 & !_LC012 & !_LC030 &
nreset & !state~1 & state~3 & state~4 & !stop
# idcnt0 & !idcnt1 & !idcnt2 & !idcnt3 & !_LC012 & !_LC030 &
nreset & !state~2 & state~3 & state~5
# !_LC012 & !_LC030 & nreset & !read & !state~1 & state~3 &
!state~4 & !stop & !write;
_EQ013 = !_LC012 & !_LC030 & nreset;
-- Node name is 'state~3~1'
-- Equation name is 'state~3~1', location is LC031, type is buried.
-- synthesized logic cell
_LC031 = LCELL( _EQ014 $ GND);
_EQ014 = nreset & !start & !state~1 & !state~2 & !state~3 & !state~4 &
!state~5 & !stop
# nreset & state~1 & state~2 & !state~3 & state~4 & !state~5
# !nreset & state~3 & !state~5
# !read & !state~1 & !state~2 & state~3 & !state~4 & !state~5 &
!write
# !state~1 & !state~2 & state~3 & !state~5 & stop;
-- Node name is 'state~3'
-- Equation name is 'state~3', location is LC002, type is buried.
state~3 = TFFE(!_EQ015, GLOBAL( clk), nreset, VCC, VCC);
_EQ015 = !_LC031 & _X008;
_X008 = EXP(!nreset & state~3 & !state~4);
-- Node name is 'state~4~1'
-- Equation name is 'state~4~1', location is LC032, type is buried.
-- synthesized logic cell
_LC032 = LCELL( _EQ016 $ GND);
_EQ016 = nreset & start & !state~1 & !state~2 & !state~3 & !state~4 &
!state~5
# !nreset & state~4 & !state~5
# idcnt0 & !idcnt1 & !idcnt2 & !idcnt3 & !state~1 & !state~2 &
state~3 & state~4 & !state~5
# nreset & read & !state~1 & !state~2 & !state~4 & !state~5 &
!stop & !write
# nreset & read & !state~1 & !state~2 & !state~3 & !state~4 &
!state~5 & !stop;
-- Node name is 'state~4'
-- Equation name is 'state~4', location is LC003, type is buried.
state~4 = TFFE(!_EQ017, GLOBAL( clk), nreset, VCC, VCC);
_EQ017 = !_LC032 & _X009 & _X010;
_X009 = EXP(!state~1 & !state~2 & state~3 & state~4 & !state~5 & stop);
_X010 = EXP(!read & state~1 & state~2 & !state~3 & state~4 & !state~5);
-- Node name is 'state~5~1'
-- Equation name is 'state~5~1', location is LC025, type is buried.
-- synthesized logic cell
_LC025 = LCELL( _EQ018 $ GND);
_EQ018 = nreset & !state~1 & !state~2 & state~3 & !state~4 & !state~5 &
!stop & write
# nreset & !state~1 & !state~2 & state~3 & state~4 & !state~5 &
stop
# nreset & !read & state~1 & state~2 & !state~3 & state~4 &
!state~5
# !state~1 & !state~2 & !state~3 & !state~4 & state~5
# idcnt0 & !idcnt1 & !idcnt2 & !idcnt3 & state~1 & !state~2 &
state~3 & !state~4 & state~5;
-- Node name is 'state~5'
-- Equation name is 'state~5', location is LC004, type is buried.
state~5 = TFFE(!_EQ019, GLOBAL( clk), nreset, VCC, VCC);
_EQ019 = !_LC025 & _X011 & _X012;
_X011 = EXP( nreset & !read & !start & !state~1 & !state~2 & !state~3 &
!state~4 & !stop);
_X012 = EXP(!nreset & !state~4 & state~5);
-- Node name is '|LPM_ADD_SUB:335|addcore:adder|addcore:adder0|gcp2' from file "addcore.tdf" line 160, column 8
-- Equation name is '_LC024', type is buried
_LC024 = LCELL( _EQ020 $ idcnt2);
_EQ020 = idcnt1 & !idcnt2;
-- Node name is '|LPM_ADD_SUB:377|addcore:adder|addcore:adder0|gcp2' from file "addcore.tdf" line 160, column 8
-- Equation name is '_LC020', type is buried
_LC020 = LCELL( _EQ021 $ idcnt2);
_EQ021 = idcnt1 & !idcnt2;
-- Node name is '~888~1'
-- Equation name is '~888~1', location is LC005, type is buried.
-- synthesized logic cell
_LC005 = LCELL( _EQ022 $ GND);
_EQ022 = !state~1 & !state~2 & state~3 & !state~5
# !iscl & !state~2 & !state~3 & state~5
# !state~1 & !state~3 & !state~4 & !state~5
# state~1 & !state~4 & state~5
# !iscl & state~4 & state~5;
-- Node name is '~960~1'
-- Equation name is '~960~1', location is LC006, type is buried.
-- synthesized logic cell
_LC006 = LCELL( _EQ023 $ GND);
_EQ023 = state~1 & !state~2 & !state~3 & !state~5
# !state~1 & state~2 & !state~3 & state~4 & !state~5
# isda & !state~1 & state~2 & state~3 & !state~4 & !state~5
# SDA & state~3 & state~4 & !state~5
# !din & state~3 & !state~4 & state~5;
-- Node name is '~1032~1'
-- Equation name is '~1032~1', location is LC023, type is buried.
-- synthesized logic cell
_LC023 = LCELL( _EQ024 $ GND);
_EQ024 = !idcnt3 & read & !state~1 & !state~2 & state~3 & !state~4 &
!state~5 & !stop
# !idcnt3 & !state~1 & !state~2 & state~3 & !state~4 & !state~5 &
!stop & write
# !idcnt3 & !start & !state~1 & !state~2 & !state~3 & !state~4 &
!state~5 & !stop
# !idcnt0 & !_LC020 & state~1 & !state~2 & state~3 & !state~4 &
state~5
# !idcnt0 & !_LC024 & !state~1 & !state~2 & state~3 & state~4 &
!state~5;
-- Node name is '~1104~1'
-- Equation name is '~1104~1', location is LC027, type is buried.
-- synthesized logic cell
_LC027 = LCELL( _EQ025 $ GND);
_EQ025 = idcnt2 & read & !state~1 & !state~2 & state~3 & !state~4 &
!state~5 & !stop
# idcnt2 & !state~1 & !state~2 & state~3 & !state~4 & !state~5 &
!stop & write
# idcnt2 & !start & !state~1 & !state~2 & !state~3 & !state~4 &
!state~5 & !stop
# !idcnt0 & !idcnt1 & state~1 & !state~2 & state~3 & !state~4 &
state~5
# !idcnt0 & !idcnt1 & !state~1 & !state~2 & state~3 & state~4 &
!state~5;
-- Node name is '~1176~1'
-- Equation name is '~1176~1', location is LC029, type is buried.
-- synthesized logic cell
_LC029 = LCELL( _EQ026 $ GND);
_EQ026 = idcnt1 & read & !state~1 & !state~2 & state~3 & !state~4 &
!state~5 & !stop
# idcnt1 & !state~1 & !state~2 & state~3 & !state~4 & !state~5 &
!stop & write
# idcnt1 & !start & !state~1 & !state~2 & !state~3 & !state~4 &
!state~5 & !stop
# idcnt1 & state~1 & state~2 & !state~3 & state~4 & !state~5
# !idcnt0 & state~1 & !state~2 & state~3 & !state~4 & state~5;
-- Node name is '~1248~1'
-- Equation name is '~1248~1', location is LC019, type is buried.
-- synthesized logic cell
_LC019 = LCELL( _EQ027 $ GND);
_EQ027 = state~1 & !state~2 & state~3 & !state~4 & state~5
# !state~1 & !state~2 & state~3 & state~4 & !state~5
# idcnt0 & !start & !state~1 & !state~2 & !state~3 & !state~4 &
!state~5 & !stop
# idcnt0 & read & !state~1 & !state~2 & state~3 & !state~5 &
!stop
# idcnt0 & !state~1 & !state~2 & state~3 & !state~5 & !stop &
write;
-- Shareable expanders that are duplicated in multiple LABs:
-- (none)
Project Information e:\电路系统设计\第11讲-i2c讲稿\i2c\i2c_core.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Standard
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'MAX7000S' family
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
PARALLEL_EXPANDERS = off
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SOFT_BUFFER_INSERTION = on
SUBFACTOR_EXTRACTION = on
TURBO_BIT = on
XOR_SYNTHESIS = on
IGNORE_SOFT_BUFFERS = off
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
One-Hot State Machine Encoding = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Use Quartus Fitter = off
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:03
Database Builder 00:00:00
Logic Synthesizer 00:00:01
Partitioner 00:00:01
Fitter 00:00:00
Timing SNF Extractor 00:00:00
Assembler 00:00:04
-------------------------- --------
Total Time 00:00:09
Memory Allocated
-----------------
Peak memory allocated during compilation = 4,273K
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