📄 i2c_core.rpt
字号:
s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
Device-Specific Information: e:\电路系统设计\第11讲-i2c讲稿\i2c\i2c_core.rpt
i2c_core
** BURIED LOGIC **
Shareable
Expanders Fan-In Fan-Out
Pin LC LAB Primitive Code Total Shared n/a INP FBK OUT FBK Name
(33) 24 B SOFT t 0 0 0 0 2 0 1 |LPM_ADD_SUB:335|addcore:adder|addcore:adder0|gcp2
(38) 20 B SOFT t 0 0 0 0 2 0 1 |LPM_ADD_SUB:377|addcore:adder|addcore:adder0|gcp2
(12) 8 A SOFT s t 1 0 1 1 5 0 1 state~1~1
(40) 18 B DFFE + t 4 0 1 4 6 0 22 state~1
(17) 12 A SOFT s t 1 0 1 0 5 0 1 state~2~1
(26) 30 B SOFT s t 0 0 0 0 5 0 1 state~2~2
(41) 17 B DFFE + t 1 0 1 4 11 0 22 state~2
(25) 31 B SOFT s t 1 0 1 5 5 0 1 state~3~1
(5) 2 A TFFE + t 1 0 0 1 3 0 23 state~3
(24) 32 B SOFT s t 1 0 1 5 9 0 1 state~4~1
(6) 3 A TFFE + t 2 0 0 3 6 0 23 state~4
(32) 25 B SOFT s t 1 0 1 4 9 0 1 state~5~1
(7) 4 A TFFE + t 2 0 0 4 6 0 24 state~5
(21) 16 A DFFE + t 1 0 1 1 6 1 0 sclo (:16)
(11) 7 A DFFE + t 0 0 0 1 2 1 0 sdao (:17)
(16) 11 A DFFE + t 1 0 1 1 6 0 1 iscl (:73)
(13) 9 A DFFE + t 0 0 0 1 2 0 1 isda (:74)
(28) 28 B TFFE + t 1 0 0 1 7 0 5 idcnt3 (:75)
(31) 26 B TFFE + t 1 0 0 1 7 0 7 idcnt2 (:76)
(36) 22 B TFFE + t 1 0 0 1 7 0 7 idcnt1 (:77)
(37) 21 B TFFE + t 1 0 0 1 7 0 9 idcnt0 (:78)
(8) 5 A SOFT s t 1 0 1 0 6 0 2 ~888~1
(9) 6 A SOFT s t 1 0 1 1 7 0 2 ~960~1
(34) 23 B SOFT s t 1 0 1 4 9 0 1 ~1032~1
(29) 27 B SOFT s t 1 0 1 4 8 0 1 ~1104~1
(27) 29 B SOFT s t 1 0 1 4 7 0 1 ~1176~1
(39) 19 B SOFT s t 1 0 1 4 6 0 1 ~1248~1
Code:
s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
Device-Specific Information: e:\电路系统设计\第11讲-i2c讲稿\i2c\i2c_core.rpt
i2c_core
** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'A':
Logic cells placed in LAB 'A'
+------------------------- LC10 SCL
| +----------------------- LC1 SDA
| | +--------------------- LC8 state~1~1
| | | +------------------- LC12 state~2~1
| | | | +----------------- LC2 state~3
| | | | | +--------------- LC3 state~4
| | | | | | +------------- LC4 state~5
| | | | | | | +----------- LC16 sclo
| | | | | | | | +--------- LC7 sdao
| | | | | | | | | +------- LC11 iscl
| | | | | | | | | | +----- LC9 isda
| | | | | | | | | | | +--- LC5 ~888~1
| | | | | | | | | | | | +- LC6 ~960~1
| | | | | | | | | | | | |
| | | | | | | | | | | | | Other LABs fed by signals
| | | | | | | | | | | | | that feed LAB 'A'
LC | | | | | | | | | | | | | | A B | Logic cells that feed LAB 'A':
LC1 -> - - - - - - - - - - - - * | * - | <-- SDA
LC2 -> - - * * * * * * - * - * * | * * | <-- state~3
LC3 -> - - * * * * * * - * - * * | * * | <-- state~4
LC4 -> - - * * - * * * * * * * * | * * | <-- state~5
LC16 -> * - - - - - - - - - - - - | * - | <-- sclo
LC7 -> - * - - - - - - - - - - - | * - | <-- sdao
LC11 -> - - - - - - - - - - - * - | * - | <-- iscl
LC9 -> - - - - - - - - - - - - * | * - | <-- isda
LC5 -> - - - - - - - * - * - - - | * - | <-- ~888~1
LC6 -> - - - - - - - - * - * - - | * - | <-- ~960~1
Pin
43 -> - - - - - - - - - - - - - | - - | <-- clk
11 -> - - - - - - - - - - - - * | * - | <-- din
6 -> * * - - * * * * * * * - - | * * | <-- nreset
9 -> - - - - - * * - - - - - - | * * | <-- read
5 -> - - * - - - * - - - - - - | * * | <-- start
8 -> - - - - - * * - - - - - - | * * | <-- stop
LC18 -> - - * * - * * * - * - * * | * * | <-- state~1
LC17 -> - - * * - * * * - * - * * | * * | <-- state~2
LC31 -> - - - - * - - - - - - - - | * - | <-- state~3~1
LC32 -> - - - - - * - - - - - - - | * - | <-- state~4~1
LC25 -> - - - - - - * - - - - - - | * - | <-- state~5~1
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).
Device-Specific Information: e:\电路系统设计\第11讲-i2c讲稿\i2c\i2c_core.rpt
i2c_core
** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'B':
Logic cells placed in LAB 'B'
+------------------------------- LC24 |LPM_ADD_SUB:335|addcore:adder|addcore:adder0|gcp2
| +----------------------------- LC20 |LPM_ADD_SUB:377|addcore:adder|addcore:adder0|gcp2
| | +--------------------------- LC18 state~1
| | | +------------------------- LC30 state~2~2
| | | | +----------------------- LC17 state~2
| | | | | +--------------------- LC31 state~3~1
| | | | | | +------------------- LC32 state~4~1
| | | | | | | +----------------- LC25 state~5~1
| | | | | | | | +--------------- LC28 idcnt3
| | | | | | | | | +------------- LC26 idcnt2
| | | | | | | | | | +----------- LC22 idcnt1
| | | | | | | | | | | +--------- LC21 idcnt0
| | | | | | | | | | | | +------- LC23 ~1032~1
| | | | | | | | | | | | | +----- LC27 ~1104~1
| | | | | | | | | | | | | | +--- LC29 ~1176~1
| | | | | | | | | | | | | | | +- LC19 ~1248~1
| | | | | | | | | | | | | | | |
| | | | | | | | | | | | | | | | Other LABs fed by signals
| | | | | | | | | | | | | | | | that feed LAB 'B'
LC | | | | | | | | | | | | | | | | | A B | Logic cells that feed LAB 'B':
LC24 -> - - - - - - - - - - - - * - - - | - * | <-- |LPM_ADD_SUB:335|addcore:adder|addcore:adder0|gcp2
LC20 -> - - - - - - - - - - - - * - - - | - * | <-- |LPM_ADD_SUB:377|addcore:adder|addcore:adder0|gcp2
LC18 -> - - * * * * * * * * * * * * * * | * * | <-- state~1
LC30 -> - - - - * - - - - - - - - - - - | - * | <-- state~2~2
LC17 -> - - * * * * * * * * * * * * * * | * * | <-- state~2
LC28 -> - - - - * - * * * - - - * - - - | - * | <-- idcnt3
LC26 -> * * - - * - * * - * - - - * - - | - * | <-- idcnt2
LC22 -> * * - - * - * * - - * - - * * - | - * | <-- idcnt1
LC21 -> - - - - * - * * - - * * * * * * | - * | <-- idcnt0
LC23 -> - - - - - - - - * - - - - - - - | - * | <-- ~1032~1
LC27 -> - - - - - - - - - * - - - - - - | - * | <-- ~1104~1
LC29 -> - - - - - - - - - - * - - - - - | - * | <-- ~1176~1
LC19 -> - - - - - - - - - - - * - - - - | - * | <-- ~1248~1
Pin
43 -> - - - - - - - - - - - - - - - - | - - | <-- clk
6 -> - - * - * * * * * * * * - - - - | * * | <-- nreset
9 -> - - * - * * * * - - - - * * * * | * * | <-- read
5 -> - - - - - * * - - - - - * * * * | * * | <-- start
8 -> - - * - * * * * - - - - * * * * | * * | <-- stop
12 -> - - * - * * * * - - - - * * * * | - * | <-- write
LC8 -> - - * - - - - - - - - - - - - - | - * | <-- state~1~1
LC12 -> - - - - * - - - - - - - - - - - | - * | <-- state~2~1
LC2 -> - - * * * * * * * * * * * * * * | * * | <-- state~3
LC3 -> - - * * * * * * * * * * * * * * | * * | <-- state~4
LC4 -> - - * * * * * * * * * * * * * * | * * | <-- state~5
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).
Device-Specific Information: e:\电路系统设计\第11讲-i2c讲稿\i2c\i2c_core.rpt
i2c_core
** EQUATIONS **
clk : INPUT;
din : INPUT;
nreset : INPUT;
read : INPUT;
start : INPUT;
stop : INPUT;
write : INPUT;
-- Node name is ':78' = 'idcnt0'
-- Equation name is 'idcnt0', location is LC021, type is buried.
idcnt0 = TFFE(!_EQ001, GLOBAL( clk), VCC, VCC, nreset);
_EQ001 = !_LC019 & _X001;
_X001 = EXP( idcnt0 & state~1 & state~2 & !state~3 & state~4 & !state~5);
-- Node name is ':77' = 'idcnt1'
-- Equation name is 'idcnt1', location is LC022, type is buried.
idcnt1 = TFFE(!_EQ002, GLOBAL( clk), VCC, VCC, nreset);
_EQ002 = !_LC029 & _X002;
_X002 = EXP(!idcnt0 & !state~1 & !state~2 & state~3 & state~4 & !state~5);
-- Node name is ':76' = 'idcnt2'
-- Equation name is 'idcnt2', location is LC026, type is buried.
idcnt2 = TFFE(!_EQ003, GLOBAL( clk), VCC, VCC, nreset);
_EQ003 = !_LC027 & _X003;
_X003 = EXP( idcnt2 & state~1 & state~2 & !state~3 & state~4 & !state~5);
-- Node name is ':75' = 'idcnt3'
-- Equation name is 'idcnt3', location is LC028, type is buried.
idcnt3 = TFFE(!_EQ004, GLOBAL( clk), VCC, VCC, nreset);
_EQ004 = !_LC023 & _X004;
_X004 = EXP(!idcnt3 & state~1 & state~2 & !state~3 & state~4 & !state~5);
-- Node name is ':73' = 'iscl'
-- Equation name is 'iscl', location is LC011, type is buried.
iscl = DFFE( _EQ005 $ !_LC005, GLOBAL( clk), VCC, VCC, nreset);
_EQ005 = !_LC005 & state~1 & state~2 & state~4 & !state~5
# !_LC005 & state~2 & !state~3 & state~4 & !state~5
# !_LC005 & state~1 & !state~2 & state~3 & !state~4;
-- Node name is ':74' = 'isda'
-- Equation name is 'isda', location is LC009, type is buried.
isda = DFFE(!_LC006 $ !state~5, GLOBAL( clk), VCC, VCC, nreset);
-- Node name is 'SCL' = ':8'
-- Equation name is 'SCL', type is bidir
SCL = TRI(_LC010, VCC);
_LC010 = DFFE( sclo $ GND, GLOBAL( clk), nreset, VCC, VCC);
-- Node name is ':16' = 'sclo'
-- Equation name is 'sclo', location is LC016, type is buried.
sclo = DFFE( _EQ006 $ !_LC005, GLOBAL( clk), VCC, VCC, nreset);
_EQ006 = !_LC005 & state~1 & state~2 & state~4 & !state~5
# !_LC005 & state~2 & !state~3 & state~4 & !state~5
# !_LC005 & state~1 & !state~2 & state~3 & !state~4;
-- Node name is 'SDA' = ':10'
-- Equation name is 'SDA', type is bidir
SDA = TRI(_LC001, VCC);
_LC001 = DFFE( sdao $ GND, GLOBAL( clk), VCC, nreset, VCC);
-- Node name is ':17' = 'sdao'
-- Equation name is 'sdao', location is LC007, type is buried.
sdao = DFFE(!_LC006 $ !state~5, GLOBAL( clk), VCC, VCC, nreset);
-- Node name is 'state~1~1'
-- Equation name is 'state~1~1', location is LC008, type is buried.
-- synthesized logic cell
_LC008 = LCELL( _EQ007 $ GND);
_EQ007 = state~1 & !state~2 & state~4 & !state~5
# state~1 & !state~3 & !state~4 & state~5
# state~1 & !state~2 & !state~3 & !state~4
# start & !state~2 & !state~3 & !state~4
# !state~2 & !state~3 & !state~4 & state~5;
-- Node name is 'state~1'
-- Equation name is 'state~1', location is LC018, type is buried.
state~1 = DFFE( _EQ008 $ _EQ009, GLOBAL( clk), nreset, VCC, VCC);
_EQ008 = !_LC008 & !read & !state~1 & state~3 & !state~4 & !state~5 &
!write & _X005 & _X006 & _X007
# !_LC008 & !state~1 & !state~2 & !state~4 & !state~5 & stop &
_X005 & _X006 & _X007
# !_LC008 & state~1 & state~3 & state~4 & !state~5 & _X005 &
_X006 & _X007;
_X005 = EXP( state~2 & state~3 & !state~4);
_X006 = EXP(!nreset & !state~5);
_X007 = EXP(!nreset & !state~4);
_EQ009 = !_LC008 & _X005 & _X006 & _X007;
_X005 = EXP( state~2 & state~3 & !state~4);
_X006 = EXP(!nreset & !state~5);
_X007 = EXP(!nreset & !state~4);
-- Node name is 'state~2~1'
-- Equation name is 'state~2~1', location is LC012, type is buried.
-- synthesized logic cell
_LC012 = LCELL( _EQ010 $ GND);
_EQ010 = state~1 & !state~3 & !state~4 & !state~5
# !state~1 & state~3 & state~5
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