📄 p2s_altera.rpt
字号:
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
Device-Specific Information: d:\vhdl\i2c\p2s_altera.rpt
p2s_altera
** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'B':
Logic cells placed in LAB 'B'
+----------------- LC17 nq
| +--------------- LC18 q
| | +------------- LC27 |74165b:u1|:95
| | | +----------- LC25 |74165b:u1|:96
| | | | +--------- LC24 |74165b:u1|:97
| | | | | +------- LC23 |74165b:u1|:98
| | | | | | +----- LC22 |74165b:u1|:99
| | | | | | | +--- LC21 |74165b:u1|:100
| | | | | | | | +- LC20 |74165b:u1|:101
| | | | | | | | |
| | | | | | | | | Other LABs fed by signals
| | | | | | | | | that feed LAB 'B'
LC | | | | | | | | | | A B | Logic cells that feed LAB 'B':
LC18 -> * * - - - - - - - | - * | <-- q
LC27 -> * * * - - - - - - | - * | <-- |74165b:u1|:95
LC25 -> - - * * - - - - - | - * | <-- |74165b:u1|:96
LC24 -> - - - * * - - - - | - * | <-- |74165b:u1|:97
LC23 -> - - - - * * - - - | - * | <-- |74165b:u1|:98
LC22 -> - - - - - * * - - | - * | <-- |74165b:u1|:99
LC21 -> - - - - - - * * - | - * | <-- |74165b:u1|:100
LC20 -> - - - - - - - * * | - * | <-- |74165b:u1|:101
Pin
43 -> - - - - - - - - - | - - | <-- clk
17 -> * * * * * * * * * | - * | <-- clkih
16 -> * * - - - - - - - | - * | <-- d0
9 -> - - * - - - - - - | - * | <-- d1
14 -> - - - * - - - - - | - * | <-- d2
18 -> - - - - * - - - - | - * | <-- d3
8 -> - - - - - * - - - | - * | <-- d4
6 -> - - - - - - * - - | - * | <-- d5
5 -> - - - - - - - * - | - * | <-- d6
4 -> - - - - - - - - * | - * | <-- d7
12 -> - - - - - - - - * | - * | <-- ser
11 -> * * * * * * * * * | - * | <-- stld
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).
Device-Specific Information: d:\vhdl\i2c\p2s_altera.rpt
p2s_altera
** EQUATIONS **
clk : INPUT;
clkih : INPUT;
d0 : INPUT;
d1 : INPUT;
d2 : INPUT;
d3 : INPUT;
d4 : INPUT;
d5 : INPUT;
d6 : INPUT;
d7 : INPUT;
ser : INPUT;
stld : INPUT;
-- Node name is 'nq' = '|74165b:u1|Q7~1'
-- Equation name is 'nq', type is output
nq = _LC017~NOT;
_LC017~NOT = DFFE( _EQ001 $ VCC, GLOBAL( clk), !_EQ002, !_EQ003, VCC);
_EQ001 = clkih & q
# !clkih & _LC027;
_EQ002 = d0 & !stld;
_EQ003 = !d0 & !stld;
-- Node name is 'q' = '|74165b:u1|Q7'
-- Equation name is 'q', type is output
q = DFFE( _EQ004 $ GND, GLOBAL( clk), !_EQ003, !_EQ002, VCC);
_EQ004 = clkih & q
# !clkih & _LC027;
-- Node name is '|74165b:u1|:95'
-- Equation name is '_LC027', type is buried
_LC027 = DFFE( _EQ005 $ GND, GLOBAL( clk), !_EQ006, !_EQ007, VCC);
_EQ005 = clkih & _LC027
# !clkih & _LC025;
_EQ006 = !d1 & !stld;
_EQ007 = d1 & !stld;
-- Node name is '|74165b:u1|:96'
-- Equation name is '_LC025', type is buried
_LC025 = DFFE( _EQ008 $ GND, GLOBAL( clk), !_EQ009, !_EQ010, VCC);
_EQ008 = clkih & _LC025
# !clkih & _LC024;
_EQ009 = !d2 & !stld;
_EQ010 = d2 & !stld;
-- Node name is '|74165b:u1|:97'
-- Equation name is '_LC024', type is buried
_LC024 = DFFE( _EQ011 $ GND, GLOBAL( clk), !_EQ012, !_EQ013, VCC);
_EQ011 = clkih & _LC024
# !clkih & _LC023;
_EQ012 = !d3 & !stld;
_EQ013 = d3 & !stld;
-- Node name is '|74165b:u1|:98'
-- Equation name is '_LC023', type is buried
_LC023 = DFFE( _EQ014 $ GND, GLOBAL( clk), !_EQ015, !_EQ016, VCC);
_EQ014 = clkih & _LC023
# !clkih & _LC022;
_EQ015 = !d4 & !stld;
_EQ016 = d4 & !stld;
-- Node name is '|74165b:u1|:99'
-- Equation name is '_LC022', type is buried
_LC022 = DFFE( _EQ017 $ GND, GLOBAL( clk), !_EQ018, !_EQ019, VCC);
_EQ017 = clkih & _LC022
# !clkih & _LC021;
_EQ018 = !d5 & !stld;
_EQ019 = d5 & !stld;
-- Node name is '|74165b:u1|:100'
-- Equation name is '_LC021', type is buried
_LC021 = DFFE( _EQ020 $ GND, GLOBAL( clk), !_EQ021, !_EQ022, VCC);
_EQ020 = clkih & _LC021
# !clkih & _LC020;
_EQ021 = !d6 & !stld;
_EQ022 = d6 & !stld;
-- Node name is '|74165b:u1|:101'
-- Equation name is '_LC020', type is buried
_LC020 = DFFE( _EQ023 $ GND, GLOBAL( clk), !_EQ024, !_EQ025, VCC);
_EQ023 = clkih & _LC020
# !clkih & ser;
_EQ024 = !d7 & !stld;
_EQ025 = d7 & !stld;
-- Shareable expanders that are duplicated in multiple LABs:
-- (none)
Project Information d:\vhdl\i2c\p2s_altera.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Standard
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'MAX7000S' family
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
PARALLEL_EXPANDERS = off
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SOFT_BUFFER_INSERTION = on
SUBFACTOR_EXTRACTION = on
TURBO_BIT = on
XOR_SYNTHESIS = on
IGNORE_SOFT_BUFFERS = off
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
One-Hot State Machine Encoding = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Use Quartus Fitter = off
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:00
Database Builder 00:00:00
Logic Synthesizer 00:00:01
Partitioner 00:00:00
Fitter 00:00:00
Timing SNF Extractor 00:00:00
Assembler 00:00:03
-------------------------- --------
Total Time 00:00:04
Memory Allocated
-----------------
Peak memory allocated during compilation = 3,456K
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