📄 shift_control.rpt
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+------------------------- LC18 din
| +----------------------- LC20 |p2s_altera:shift|74165b:u1|:95
| | +--------------------- LC26 |p2s_altera:shift|74165b:u1|:96
| | | +------------------- LC22 |p2s_altera:shift|74165b:u1|:97
| | | | +----------------- LC21 |p2s_altera:shift|74165b:u1|:98
| | | | | +--------------- LC28 |p2s_altera:shift|74165b:u1|:99
| | | | | | +------------- LC19 |p2s_altera:shift|74165b:u1|:100
| | | | | | | +----------- LC17 |p2s_altera:shift|74165b:u1|:101
| | | | | | | | +--------- LC29 iclkih
| | | | | | | | | +------- LC27 istld
| | | | | | | | | | +----- LC25 iser
| | | | | | | | | | | +--- LC24 shift_state1
| | | | | | | | | | | | +- LC23 shift_state0
| | | | | | | | | | | | |
| | | | | | | | | | | | | Other LABs fed by signals
| | | | | | | | | | | | | that feed LAB 'B'
LC | | | | | | | | | | | | | | A B | Logic cells that feed LAB 'B':
LC18 -> * - - - - - - - - - - - - | - * | <-- din
LC20 -> * * - - - - - - - - - - - | - * | <-- |p2s_altera:shift|74165b:u1|:95
LC26 -> - * * - - - - - - - - - - | - * | <-- |p2s_altera:shift|74165b:u1|:96
LC22 -> - - * * - - - - - - - - - | - * | <-- |p2s_altera:shift|74165b:u1|:97
LC21 -> - - - * * - - - - - - - - | - * | <-- |p2s_altera:shift|74165b:u1|:98
LC28 -> - - - - * * - - - - - - - | - * | <-- |p2s_altera:shift|74165b:u1|:99
LC19 -> - - - - - * * - - - - - - | - * | <-- |p2s_altera:shift|74165b:u1|:100
LC17 -> - - - - - - * * - - - - - | - * | <-- |p2s_altera:shift|74165b:u1|:101
LC29 -> * * * * * * * * - - - - - | - * | <-- iclkih
LC27 -> * * * * * * * * - - - - - | - * | <-- istld
LC25 -> - - - - - - - * - - - - - | - * | <-- iser
LC24 -> - - - - - - - - * * * * * | - * | <-- shift_state1
LC23 -> - - - - - - - - * * * * * | - * | <-- shift_state0
Pin
43 -> - - - - - - - - - - - - - | - - | <-- clk
12 -> - - - - - - - - - - - * - | - * | <-- dcnt0
14 -> - - - - - - - - - - - * - | - * | <-- dcnt1
16 -> - - - - - - - - - - - * - | - * | <-- dcnt2
18 -> - - - - - - - - - - - * - | - * | <-- dcnt3
20 -> - - - - - - - * - - - - - | - * | <-- d0
19 -> - - - - - - * - - - - - - | - * | <-- d1
11 -> - - - - - * - - - - - - - | - * | <-- d2
9 -> - - - - * - - - - - - - - | - * | <-- d3
8 -> - - - * - - - - - - - - - | - * | <-- d4
6 -> - - * - - - - - - - - - - | - * | <-- d5
5 -> - * - - - - - - - - - - - | - * | <-- d6
4 -> * - - - - - - - - - - - - | - * | <-- d7
17 -> - - - - - - - - - - - * * | - * | <-- iflag
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).
Device-Specific Information: d:\vhdl\i2c讲稿\i2c\shift_control.rpt
shift_control
** EQUATIONS **
clk : INPUT;
dcnt0 : INPUT;
dcnt1 : INPUT;
dcnt2 : INPUT;
dcnt3 : INPUT;
d0 : INPUT;
d1 : INPUT;
d2 : INPUT;
d3 : INPUT;
d4 : INPUT;
d5 : INPUT;
d6 : INPUT;
d7 : INPUT;
iflag : INPUT;
-- Node name is 'din' = '|p2s_altera:shift|74165b:u1|Q7'
-- Equation name is 'din', type is output
din = DFFE( _EQ001 $ GND, GLOBAL( clk), !_EQ002, !_EQ003, VCC);
_EQ001 = din & iclkih
# !iclkih & _LC020;
_EQ002 = !d7 & !istld;
_EQ003 = d7 & !istld;
-- Node name is ':16' = 'iclkih'
-- Equation name is 'iclkih', location is LC029, type is buried.
iclkih = DFFE( _EQ004 $ GND, GLOBAL( clk), VCC, VCC, VCC);
_EQ004 = shift_state0 & !shift_state1;
-- Node name is ':18' = 'iser'
-- Equation name is 'iser', location is LC025, type is buried.
iser = DFFE( _EQ005 $ shift_state1, GLOBAL( clk), VCC, VCC, VCC);
_EQ005 = shift_state0 & !shift_state1;
-- Node name is ':17' = 'istld'
-- Equation name is 'istld', location is LC027, type is buried.
istld = DFFE( _EQ006 $ shift_state1, GLOBAL( clk), VCC, VCC, VCC);
_EQ006 = shift_state0 & !shift_state1;
-- Node name is ':21' = 'shift_state0'
-- Equation name is 'shift_state0', location is LC023, type is buried.
shift_state0 = DFFE( _EQ007 $ VCC, GLOBAL( clk), VCC, VCC, VCC);
_EQ007 = iflag & shift_state0 & !shift_state1;
-- Node name is ':20' = 'shift_state1'
-- Equation name is 'shift_state1', location is LC024, type is buried.
shift_state1 = TFFE(!_EQ008, GLOBAL( clk), VCC, VCC, VCC);
_EQ008 = !dcnt0 & !dcnt1 & !dcnt2 & dcnt3 & !shift_state1
# !shift_state0 & !shift_state1
# !iflag & !shift_state1;
-- Node name is '|p2s_altera:shift|74165b:u1|:95'
-- Equation name is '_LC020', type is buried
_LC020 = DFFE( _EQ009 $ GND, GLOBAL( clk), !_EQ010, !_EQ011, VCC);
_EQ009 = iclkih & _LC020
# !iclkih & _LC026;
_EQ010 = !d6 & !istld;
_EQ011 = d6 & !istld;
-- Node name is '|p2s_altera:shift|74165b:u1|:96'
-- Equation name is '_LC026', type is buried
_LC026 = DFFE( _EQ012 $ GND, GLOBAL( clk), !_EQ013, !_EQ014, VCC);
_EQ012 = iclkih & _LC026
# !iclkih & _LC022;
_EQ013 = !d5 & !istld;
_EQ014 = d5 & !istld;
-- Node name is '|p2s_altera:shift|74165b:u1|:97'
-- Equation name is '_LC022', type is buried
_LC022 = DFFE( _EQ015 $ GND, GLOBAL( clk), !_EQ016, !_EQ017, VCC);
_EQ015 = iclkih & _LC022
# !iclkih & _LC021;
_EQ016 = !d4 & !istld;
_EQ017 = d4 & !istld;
-- Node name is '|p2s_altera:shift|74165b:u1|:98'
-- Equation name is '_LC021', type is buried
_LC021 = DFFE( _EQ018 $ GND, GLOBAL( clk), !_EQ019, !_EQ020, VCC);
_EQ018 = iclkih & _LC021
# !iclkih & _LC028;
_EQ019 = !d3 & !istld;
_EQ020 = d3 & !istld;
-- Node name is '|p2s_altera:shift|74165b:u1|:99'
-- Equation name is '_LC028', type is buried
_LC028 = DFFE( _EQ021 $ GND, GLOBAL( clk), !_EQ022, !_EQ023, VCC);
_EQ021 = iclkih & _LC028
# !iclkih & _LC019;
_EQ022 = !d2 & !istld;
_EQ023 = d2 & !istld;
-- Node name is '|p2s_altera:shift|74165b:u1|:100'
-- Equation name is '_LC019', type is buried
_LC019 = DFFE( _EQ024 $ GND, GLOBAL( clk), !_EQ025, !_EQ026, VCC);
_EQ024 = iclkih & _LC019
# !iclkih & _LC017;
_EQ025 = !d1 & !istld;
_EQ026 = d1 & !istld;
-- Node name is '|p2s_altera:shift|74165b:u1|:101'
-- Equation name is '_LC017', type is buried
_LC017 = DFFE( _EQ027 $ GND, GLOBAL( clk), !_EQ028, !_EQ029, VCC);
_EQ027 = iclkih & _LC017
# !iclkih & iser;
_EQ028 = !d0 & !istld;
_EQ029 = d0 & !istld;
-- Shareable expanders that are duplicated in multiple LABs:
-- (none)
Project Information d:\vhdl\i2c讲稿\i2c\shift_control.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Standard
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'MAX7000S' family
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
PARALLEL_EXPANDERS = off
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SOFT_BUFFER_INSERTION = on
SUBFACTOR_EXTRACTION = on
TURBO_BIT = on
XOR_SYNTHESIS = on
IGNORE_SOFT_BUFFERS = off
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
One-Hot State Machine Encoding = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Use Quartus Fitter = off
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:01
Database Builder 00:00:00
Logic Synthesizer 00:00:00
Partitioner 00:00:00
Fitter 00:00:00
Timing SNF Extractor 00:00:00
Assembler 00:00:03
-------------------------- --------
Total Time 00:00:04
Memory Allocated
-----------------
Peak memory allocated during compilation = 3,582K
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