📄 i2c_write.rpt
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_LC064 = LCELL( _EQ029 $ GND);
_EQ029 = nreset & start & !state~1 & !state~2 & !state~3 & !state~4 &
!state~5
# !nreset & state~4 & !state~5
# idcnt0 & !idcnt1 & !idcnt2 & !idcnt3 & !state~1 & !state~2 &
state~3 & state~4 & !state~5
# nreset & read & !state~1 & !state~2 & !state~4 & !state~5 &
!stop & !write
# nreset & read & !state~1 & !state~2 & !state~3 & !state~4 &
!state~5 & !stop;
-- Node name is 'state~4'
-- Equation name is 'state~4', location is LC037, type is buried.
state~4 = TFFE(!_EQ030, GLOBAL( clk), nreset, VCC, VCC);
_EQ030 = !_LC064 & _X023 & _X024;
_X023 = EXP(!state~1 & !state~2 & state~3 & state~4 & !state~5 & stop);
_X024 = EXP(!read & state~1 & state~2 & !state~3 & state~4 & !state~5);
-- Node name is 'state~5~1'
-- Equation name is 'state~5~1', location is LC063, type is buried.
-- synthesized logic cell
_LC063 = LCELL( _EQ031 $ GND);
_EQ031 = nreset & !state~1 & !state~2 & state~3 & !state~4 & !state~5 &
!stop & write
# nreset & !state~1 & !state~2 & state~3 & state~4 & !state~5 &
stop
# nreset & !read & state~1 & state~2 & !state~3 & state~4 &
!state~5
# !state~1 & !state~2 & !state~3 & !state~4 & state~5
# idcnt0 & !idcnt1 & !idcnt2 & !idcnt3 & state~1 & !state~2 &
state~3 & !state~4 & state~5;
-- Node name is 'state~5'
-- Equation name is 'state~5', location is LC036, type is buried.
state~5 = TFFE(!_EQ032, GLOBAL( clk), nreset, VCC, VCC);
_EQ032 = !_LC063 & _X025 & _X026;
_X025 = EXP( nreset & !read & !start & !state~1 & !state~2 & !state~3 &
!state~4 & !stop);
_X026 = EXP(!nreset & !state~4 & state~5);
-- Node name is '|LPM_ADD_SUB:342|addcore:adder|addcore:adder0|gcp2' from file "addcore.tdf" line 160, column 8
-- Equation name is '_LC054', type is buried
_LC054 = LCELL( _EQ033 $ idcnt2);
_EQ033 = idcnt1 & !idcnt2;
-- Node name is '|LPM_ADD_SUB:384|addcore:adder|addcore:adder0|gcp2' from file "addcore.tdf" line 160, column 8
-- Equation name is '_LC060', type is buried
_LC060 = LCELL( _EQ034 $ idcnt2);
_EQ034 = idcnt1 & !idcnt2;
-- Node name is '|p2s_altera:shift|74165b:u1|:95'
-- Equation name is '_LC030', type is buried
_LC030 = DFFE( _EQ035 $ GND, GLOBAL( clk), !_EQ036, !_EQ037, VCC);
_EQ035 = iclkih & _LC030
# !iclkih & _LC023;
_EQ036 = !d6 & !istld;
_EQ037 = d6 & !istld;
-- Node name is '|p2s_altera:shift|74165b:u1|:96'
-- Equation name is '_LC023', type is buried
_LC023 = DFFE( _EQ038 $ GND, GLOBAL( clk), !_EQ039, !_EQ040, VCC);
_EQ038 = iclkih & _LC023
# !iclkih & _LC022;
_EQ039 = !d5 & !istld;
_EQ040 = d5 & !istld;
-- Node name is '|p2s_altera:shift|74165b:u1|:97'
-- Equation name is '_LC022', type is buried
_LC022 = DFFE( _EQ041 $ GND, GLOBAL( clk), !_EQ042, !_EQ043, VCC);
_EQ041 = iclkih & _LC022
# !iclkih & _LC025;
_EQ042 = !d4 & !istld;
_EQ043 = d4 & !istld;
-- Node name is '|p2s_altera:shift|74165b:u1|:98'
-- Equation name is '_LC025', type is buried
_LC025 = DFFE( _EQ044 $ GND, GLOBAL( clk), !_EQ045, !_EQ046, VCC);
_EQ044 = iclkih & _LC025
# !iclkih & _LC029;
_EQ045 = !d3 & !istld;
_EQ046 = d3 & !istld;
-- Node name is '|p2s_altera:shift|74165b:u1|:99'
-- Equation name is '_LC029', type is buried
_LC029 = DFFE( _EQ047 $ GND, GLOBAL( clk), !_EQ048, !_EQ049, VCC);
_EQ047 = iclkih & _LC029
# !iclkih & _LC031;
_EQ048 = !d2 & !istld;
_EQ049 = d2 & !istld;
-- Node name is '|p2s_altera:shift|74165b:u1|:100'
-- Equation name is '_LC031', type is buried
_LC031 = DFFE( _EQ050 $ GND, GLOBAL( clk), !_EQ051, !_EQ052, VCC);
_EQ050 = iclkih & _LC031
# !iclkih & _LC032;
_EQ051 = !d1 & !istld;
_EQ052 = d1 & !istld;
-- Node name is '|p2s_altera:shift|74165b:u1|:101'
-- Equation name is '_LC032', type is buried
_LC032 = DFFE( _EQ053 $ GND, GLOBAL( clk), !_EQ054, !_EQ055, VCC);
_EQ053 = iclkih & _LC032
# !iclkih & iser;
_EQ054 = !d0 & !istld;
_EQ055 = d0 & !istld;
-- Node name is '~1039~1'
-- Equation name is '~1039~1', location is LC059, type is buried.
-- synthesized logic cell
_LC059 = LCELL( _EQ056 $ GND);
_EQ056 = !idcnt3 & read & !state~1 & !state~2 & state~3 & !state~4 &
!state~5 & !stop
# !idcnt3 & !state~1 & !state~2 & state~3 & !state~4 & !state~5 &
!stop & write
# !idcnt3 & !start & !state~1 & !state~2 & !state~3 & !state~4 &
!state~5 & !stop
# !idcnt0 & !_LC060 & state~1 & !state~2 & state~3 & !state~4 &
state~5
# !idcnt0 & !_LC054 & !state~1 & !state~2 & state~3 & state~4 &
!state~5;
-- Node name is '~1111~1'
-- Equation name is '~1111~1', location is LC058, type is buried.
-- synthesized logic cell
_LC058 = LCELL( _EQ057 $ GND);
_EQ057 = idcnt2 & read & !state~1 & !state~2 & state~3 & !state~4 &
!state~5 & !stop
# idcnt2 & !state~1 & !state~2 & state~3 & !state~4 & !state~5 &
!stop & write
# idcnt2 & !start & !state~1 & !state~2 & !state~3 & !state~4 &
!state~5 & !stop
# !idcnt0 & !idcnt1 & state~1 & !state~2 & state~3 & !state~4 &
state~5
# !idcnt0 & !idcnt1 & !state~1 & !state~2 & state~3 & state~4 &
!state~5;
-- Node name is '~1183~1'
-- Equation name is '~1183~1', location is LC056, type is buried.
-- synthesized logic cell
_LC056 = LCELL( _EQ058 $ GND);
_EQ058 = idcnt1 & read & !state~1 & !state~2 & state~3 & !state~4 &
!state~5 & !stop
# idcnt1 & !state~1 & !state~2 & state~3 & !state~4 & !state~5 &
!stop & write
# idcnt1 & !start & !state~1 & !state~2 & !state~3 & !state~4 &
!state~5 & !stop
# idcnt1 & state~1 & state~2 & !state~3 & state~4 & !state~5
# !idcnt0 & state~1 & !state~2 & state~3 & !state~4 & state~5;
-- Node name is '~1255~1'
-- Equation name is '~1255~1', location is LC055, type is buried.
-- synthesized logic cell
_LC055 = LCELL( _EQ059 $ GND);
_EQ059 = state~1 & !state~2 & state~3 & !state~4 & state~5
# !state~1 & !state~2 & state~3 & state~4 & !state~5
# idcnt0 & !start & !state~1 & !state~2 & !state~3 & !state~4 &
!state~5 & !stop
# idcnt0 & read & !state~1 & !state~2 & state~3 & !state~5 &
!stop
# idcnt0 & !state~1 & !state~2 & state~3 & !state~5 & !stop &
write;
-- Shareable expanders that are duplicated in multiple LABs:
-- (none)
Project Information e:\电路系统设计\第11讲-i2c讲稿\i2c\i2c_write.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Standard
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'MAX7000S' family
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
PARALLEL_EXPANDERS = off
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SOFT_BUFFER_INSERTION = on
SUBFACTOR_EXTRACTION = on
TURBO_BIT = on
XOR_SYNTHESIS = on
IGNORE_SOFT_BUFFERS = off
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
One-Hot State Machine Encoding = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Use Quartus Fitter = off
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:01
Database Builder 00:00:01
Logic Synthesizer 00:00:01
Partitioner 00:00:00
Fitter 00:00:01
Timing SNF Extractor 00:00:00
Assembler 00:00:04
-------------------------- --------
Total Time 00:00:08
Memory Allocated
-----------------
Peak memory allocated during compilation = 5,114K
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