📄 i2c_write.rpt
字号:
r = Fitter-inserted logic cell
G = Global Source. Fan-out destinations counted here do not include destinations
that are driven using global routing resources. Refer to the Auto Global Signals,
Clock Signals, Clear Signals, Synchronous Load Signals, and Synchronous Clear Signals
Sections of this Report File for information on which signals' fan-outs are used as
Clock, Clear, Preset, Output Enable, and synchronous Load signals.
Device-Specific Information: e:\电路系统设计\第11讲-i2c讲稿\i2c\i2c_write.rpt
i2c_write
** OUTPUTS **
Shareable
Expanders Fan-In Fan-Out
Pin LC LAB Primitive Code Total Shared n/a INP FBK OUT FBK Name
41 17 B FF + t 0 0 0 1 4 1 2 dout (|p2s_altera:shift|74165b:u1|:94)
46 35 C FF + t 0 0 0 1 1 0 0 SCL
51 39 C FF + t 0 0 0 1 1 0 0 SDA
Code:
s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
Device-Specific Information: e:\电路系统设计\第11讲-i2c讲稿\i2c\i2c_write.rpt
i2c_write
** BURIED LOGIC **
Shareable
Expanders Fan-In Fan-Out
Pin LC LAB Primitive Code Total Shared n/a INP FBK OUT FBK Name
(69) 54 D SOFT t 0 0 0 0 2 0 1 |LPM_ADD_SUB:342|addcore:adder|addcore:adder0|gcp2
(76) 60 D SOFT t 0 0 0 0 2 0 1 |LPM_ADD_SUB:384|addcore:adder|addcore:adder0|gcp2
(25) 30 B DFFE + t 0 0 0 1 4 1 1 |p2s_altera:shift|74165b:u1|:95
(34) 23 B DFFE + t 0 0 0 1 4 0 2 |p2s_altera:shift|74165b:u1|:96
(35) 22 B DFFE + t 0 0 0 1 4 0 2 |p2s_altera:shift|74165b:u1|:97
(31) 25 B DFFE + t 0 0 0 1 4 0 2 |p2s_altera:shift|74165b:u1|:98
(27) 29 B DFFE + t 0 0 0 1 4 0 2 |p2s_altera:shift|74165b:u1|:99
(24) 31 B DFFE + t 0 0 0 1 4 0 2 |p2s_altera:shift|74165b:u1|:100
(23) 32 B DFFE + t 0 0 0 1 4 0 2 |p2s_altera:shift|74165b:u1|:101
(77) 61 D SOFT s t 1 0 1 1 5 0 1 state~1~1
(44) 33 C DFFE + t 4 0 1 4 6 0 22 state~1
(52) 40 C SOFT s t 1 0 1 0 5 0 1 state~2~1
(63) 49 D DFFE + t 4 0 1 4 10 0 22 state~2
(79) 62 D SOFT s t 1 0 1 5 5 0 1 state~3~1
(40) 18 B TFFE + t 1 0 0 1 3 0 23 state~3
(81) 64 D SOFT s t 1 0 1 5 9 0 1 state~4~1
(49) 37 C TFFE + t 2 0 0 3 6 0 23 state~4
(80) 63 D SOFT s t 1 0 1 4 9 0 1 state~5~1
(48) 36 C TFFE + t 2 0 0 4 6 0 22 state~5
(61) 47 C DFFE + t 0 0 0 0 2 1 7 iclkih (:20)
(60) 46 C DFFE + t 0 0 0 0 2 1 7 istld (:21)
(58) 45 C DFFE + t 0 0 0 0 2 0 1 iser (:22)
(57) 44 C DFFE + t 0 0 0 1 1 0 1 dcnt3 (:25)
(56) 43 C DFFE + t 0 0 0 1 1 0 2 dcnt2 (:26)
(65) 51 D DFFE + t 0 0 0 1 1 0 2 dcnt1 (:27)
(64) 50 D DFFE + t 0 0 0 1 1 0 2 dcnt0 (:28)
(54) 41 C DFFE + t 6 5 1 1 6 1 0 sclo (:29)
(28) 28 B DFFE + t 5 5 0 1 7 1 0 sdao (:30)
(73) 57 D DFFE + t 2 0 1 1 10 0 3 iflag (:33)
(55) 42 C TFFE + t 0 0 0 0 6 0 5 shift_state1 (:34)
(45) 34 C DFFE + t 0 0 0 0 7 0 5 shift_state0 (:35)
(50) 38 C DFFE + t 6 5 1 1 6 0 2 iscl (:88)
(36) 21 B DFFE + t 5 5 0 1 7 0 2 isda (:89)
(68) 53 D TFFE + t 1 0 0 1 7 0 7 idcnt3 (:90)
(67) 52 D TFFE + t 1 0 0 1 7 0 9 idcnt2 (:91)
(37) 20 B TFFE + t 1 0 0 1 7 0 9 idcnt1 (:92)
(29) 27 B TFFE + t 1 0 0 1 7 0 11 idcnt0 (:93)
(75) 59 D SOFT s t 1 0 1 4 9 0 1 ~1039~1
(74) 58 D SOFT s t 1 0 1 4 8 0 1 ~1111~1
(71) 56 D SOFT s t 1 0 1 4 7 0 1 ~1183~1
(70) 55 D SOFT s t 1 0 1 4 6 0 1 ~1255~1
Code:
s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
Device-Specific Information: e:\电路系统设计\第11讲-i2c讲稿\i2c\i2c_write.rpt
i2c_write
** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'B':
Logic cells placed in LAB 'B'
+------------------------- LC17 dout
| +----------------------- LC30 |p2s_altera:shift|74165b:u1|:95
| | +--------------------- LC23 |p2s_altera:shift|74165b:u1|:96
| | | +------------------- LC22 |p2s_altera:shift|74165b:u1|:97
| | | | +----------------- LC25 |p2s_altera:shift|74165b:u1|:98
| | | | | +--------------- LC29 |p2s_altera:shift|74165b:u1|:99
| | | | | | +------------- LC31 |p2s_altera:shift|74165b:u1|:100
| | | | | | | +----------- LC32 |p2s_altera:shift|74165b:u1|:101
| | | | | | | | +--------- LC18 state~3
| | | | | | | | | +------- LC28 sdao
| | | | | | | | | | +----- LC21 isda
| | | | | | | | | | | +--- LC20 idcnt1
| | | | | | | | | | | | +- LC27 idcnt0
| | | | | | | | | | | | |
| | | | | | | | | | | | | Other LABs fed by signals
| | | | | | | | | | | | | that feed LAB 'B'
LC | | | | | | | | | | | | | | A B C D | Logic cells that feed LAB 'B':
LC17 -> * - - - - - - - - * * - - | - * - - | <-- dout
LC30 -> * * - - - - - - - - - - - | - * - - | <-- |p2s_altera:shift|74165b:u1|:95
LC23 -> - * * - - - - - - - - - - | - * - - | <-- |p2s_altera:shift|74165b:u1|:96
LC22 -> - - * * - - - - - - - - - | - * - - | <-- |p2s_altera:shift|74165b:u1|:97
LC25 -> - - - * * - - - - - - - - | - * - - | <-- |p2s_altera:shift|74165b:u1|:98
LC29 -> - - - - * * - - - - - - - | - * - - | <-- |p2s_altera:shift|74165b:u1|:99
LC31 -> - - - - - * * - - - - - - | - * - - | <-- |p2s_altera:shift|74165b:u1|:100
LC32 -> - - - - - - * * - - - - - | - * - - | <-- |p2s_altera:shift|74165b:u1|:101
LC18 -> - - - - - - - - * * * * * | - * * * | <-- state~3
LC21 -> - - - - - - - - - * * - - | - * - - | <-- isda
LC27 -> - - - - - - - - - - - * * | - * - * | <-- idcnt0
Pin
83 -> - - - - - - - - - - - - - | - - - - | <-- clk
12 -> - - - - - - - * - - - - - | - * - - | <-- d0
10 -> - - - - - - * - - - - - - | - * - - | <-- d1
9 -> - - - - - * - - - - - - - | - * - - | <-- d2
8 -> - - - - * - - - - - - - - | - * - - | <-- d3
6 -> - - - * - - - - - - - - - | - * - - | <-- d4
11 -> - - * - - - - - - - - - - | - * - - | <-- d5
15 -> - * - - - - - - - - - - - | - * - - | <-- d6
16 -> * - - - - - - - - - - - - | - * - - | <-- d7
22 -> - - - - - - - - * * * * * | - * * * | <-- nreset
LC33 -> - - - - - - - - - * * * * | - * * * | <-- state~1
LC49 -> - - - - - - - - - * * * * | - * * * | <-- state~2
LC62 -> - - - - - - - - * - - - - | - * - - | <-- state~3~1
LC37 -> - - - - - - - - * * * * * | - * * * | <-- state~4
LC36 -> - - - - - - - - - * * * * | - * * * | <-- state~5
LC47 -> * * * * * * * * - - - - - | - * - - | <-- iclkih
LC46 -> * * * * * * * * - - - - - | - * - - | <-- istld
LC45 -> - - - - - - - * - - - - - | - * - - | <-- iser
LC56 -> - - - - - - - - - - - * - | - * - - | <-- ~1183~1
LC55 -> - - - - - - - - - - - - * | - * - - | <-- ~1255~1
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).
Device-Specific Information: e:\电路系统设计\第11讲-i2c讲稿\i2c\i2c_write.rpt
i2c_write
** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'C':
Logic cells placed in LAB 'C'
+----------------------------- LC35 SCL
| +--------------------------- LC39 SDA
| | +------------------------- LC33 state~1
| | | +----------------------- LC40 state~2~1
| | | | +--------------------- LC37 state~4
| | | | | +------------------- LC36 state~5
| | | | | | +----------------- LC47 iclkih
| | | | | | | +--------------- LC46 istld
| | | | | | | | +------------- LC45 iser
| | | | | | | | | +----------- LC44 dcnt3
| | | | | | | | | | +--------- LC43 dcnt2
| | | | | | | | | | | +------- LC41 sclo
| | | | | | | | | | | | +----- LC42 shift_state1
| | | | | | | | | | | | | +--- LC34 shift_state0
| | | | | | | | | | | | | | +- LC38 iscl
| | | | | | | | | | | | | | |
| | | | | | | | | | | | | | | Other LABs fed by signals
| | | | | | | | | | | | | | | that feed LAB 'C'
LC | | | | | | | | | | | | | | | | A B C D | Logic cells that feed LAB 'C':
LC33 -> - - * * * * - - - - - * - - * | - * * * | <-- state~1
LC37 -> - - * * * * - - - - - * - - * | - * * * | <-- state~4
LC36 -> - - * * * * - - - - - * - - * | - * * * | <-- state~5
LC44 -> - - - - - - - - - - - - - * - | - - * - | <-- dcnt3
LC43 -> - - - - - - - - - - - - * * - | - - * - | <-- dcnt2
LC41 -> * - - - - - - - - - - - - - - | - - * - | <-- sclo
LC42 -> - - - - - - * * * - - - * * - | - - * - | <-- shift_state1
LC34 -> - - - - - - * * * - - - * * - | - - * - | <-- shift_state0
LC38 -> - - - - - - - - - - - * - - * | - - * - | <-- iscl
Pin
83 -> - - - - - - - - - - - - - - - | - - - - | <-- clk
22 -> * * * - * * - - - * * * - - * | - * * * | <-- nreset
20 -> - - * - * * - - - - - - - - - | - - * * | <-- read
21 -> - - - - - * - - - - - - - - - | - - * * | <-- start
18 -> - - * - * * - - - - - - - - - | - - * * | <-- stop
17 -> - - * - - - - - - - - - - - - | - - * * | <-- write
LC61 -> - - * - - - - - - - - - - - - | - - * - | <-- state~1~1
LC49 -> - - * * * * - - - - - * - - * | - * * * | <-- state~2
LC18 -> - - * * * * - - - - - * - - * | - * * * | <-- state~3
LC64 -> - - - - * - - - - - - - - - - | - - * - | <-- state~4~1
LC63 -> - - - - - * - - - - - - - - - | - - * - | <-- state~5~1
LC51 -> - - - - - - - - - - - - * * - | - - * - | <-- dcnt1
LC50 -> - - - - - - - - - - - - * * - | - - * - | <-- dcnt0
LC28 -> - * - - - - - - - - - - - - - | - - * - | <-- sdao
LC57 -> - - - - - - - - - - - - * * - | - - * * | <-- iflag
LC53 -> - - - - - - - - - * - - - - - | - - * * | <-- idcnt3
LC52 -> - - - - - - - - - - * - - - - | - - * * | <-- idcnt2
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).
Device-Specific Information: e:\电路系统设计\第11讲-i2c讲稿\i2c\i2c_write.rpt
i2c_write
** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'D':
Logic cells placed in LAB 'D'
+------------------------------- LC54 |LPM_ADD_SUB:342|addcore:adder|addcore:adder0|gcp2
| +----------------------------- LC60 |LPM_ADD_SUB:384|addcore:adder|addcore:adder0|gcp2
| | +--------------------------- LC61 state~1~1
| | | +------------------------- LC49 state~2
| | | | +----------------------- LC62 state~3~1
| | | | | +--------------------- LC64 state~4~1
| | | | | | +------------------- LC63 state~5~1
| | | | | | | +----------------- LC51 dcnt1
| | | | | | | | +--------------- LC50 dcnt0
| | | | | | | | | +------------- LC57 iflag
| | | | | | | | | | +----------- LC53 idcnt3
| | | | | | | | | | | +--------- LC52 idcnt2
| | | | | | | | | | | | +------- LC59 ~1039~1
| | | | | | | | | | | | | +----- LC58 ~1111~1
| | | | | | | | | | | | | | +--- LC56 ~1183~1
| | | | | | | | | | | | | | | +- LC55 ~1255~1
| | | | | | | | | | | | | | | |
| | | | | | | | | | | | | | | | Other LABs fed by signals
| | | | | | | | | | | | | | | | that feed LAB 'D'
LC | | | | | | | | | | | | | | | | | A B C D | Logic cells that feed LAB 'D':
LC54 -> - - - - - - - - - - - - * - - - | - - - * | <-- |LPM_ADD_SUB:342|addcore:adder|addcore:adder0|gcp2
LC60 -> - - - - - - - - - - - - * - - - | - - - * | <-- |LPM_ADD_SUB:384|addcore:adder|addcore:adder0|gcp2
LC49 -> - - * * * * * - - * * * * * * * | - * * * | <-- state~2
LC57 -> - - - - - - - - - * - - - - - - | - - * * | <-- iflag
LC53 -> - - - * - * * - - * * - * - - - | - - * * | <-- idcnt3
LC52 -> * * - * - * * - - * - * - * - - | - - * * | <-- idcnt2
LC59 -> - - - - - - - - - - * - - - - - | - - - * | <-- ~1039~1
LC58 -> - - - - - - - - - - - * - - - - | - - - * | <-- ~1111~1
Pin
83 -> - - - - - - - - - - - - - - - - | - - - - | <-- clk
22 -> - - - * * * * * * * * * - - - - | - * * * | <-- nreset
20 -> - - - * * * * - - - - - * * * * | - - * * | <-- read
21 -> - - * - * * - - - - - - * * * * | - - * * | <-- start
18 -> - - - * * * * - - - - - * * * * | - - * * | <-- stop
17 -> - - - * * * * - - - - - * * * * | - - * * | <-- write
LC33 -> - - * * * * * - - * * * * * * * | - * * * | <-- state~1
LC40 -> - - - * - - - - - - - - - - - - | - - - * | <-- state~2~1
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -