📄 i2c1.rpt
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!write
# !state~1 & !state~2 & state~3 & !state~5 & stop;
-- Node name is 'state~3'
-- Equation name is 'state~3', location is LC038, type is buried.
state~3 = TFFE(!_EQ046, GLOBAL( clk), nreset, VCC, VCC);
_EQ046 = !_LC045 & _X036;
_X036 = EXP(!nreset & state~3 & !state~4);
-- Node name is 'state~4~1'
-- Equation name is 'state~4~1', location is LC051, type is buried.
-- synthesized logic cell
_LC051 = LCELL( _EQ047 $ GND);
_EQ047 = nreset & start & !state~1 & !state~2 & !state~3 & !state~4 &
!state~5
# !nreset & state~4 & !state~5
# idcnt0 & !idcnt1 & !idcnt2 & !idcnt3 & !state~1 & !state~2 &
state~3 & state~4 & !state~5
# nreset & read & !state~1 & !state~2 & !state~4 & !state~5 &
!stop & !write
# nreset & read & !state~1 & !state~2 & !state~3 & !state~4 &
!state~5 & !stop;
-- Node name is 'state~4'
-- Equation name is 'state~4', location is LC044, type is buried.
state~4 = TFFE(!_EQ048, GLOBAL( clk), nreset, VCC, VCC);
_EQ048 = !_LC051 & _X037 & _X038;
_X037 = EXP(!state~1 & !state~2 & state~3 & state~4 & !state~5 & stop);
_X038 = EXP(!read & state~1 & state~2 & !state~3 & state~4 & !state~5);
-- Node name is 'state~5~1'
-- Equation name is 'state~5~1', location is LC061, type is buried.
-- synthesized logic cell
_LC061 = LCELL( _EQ049 $ GND);
_EQ049 = nreset & !state~1 & !state~2 & state~3 & !state~4 & !state~5 &
!stop & write
# nreset & !state~1 & !state~2 & state~3 & state~4 & !state~5 &
stop
# nreset & !read & state~1 & state~2 & !state~3 & state~4 &
!state~5
# !state~1 & !state~2 & !state~3 & !state~4 & state~5
# idcnt0 & !idcnt1 & !idcnt2 & !idcnt3 & state~1 & !state~2 &
state~3 & !state~4 & state~5;
-- Node name is 'state~5'
-- Equation name is 'state~5', location is LC035, type is buried.
state~5 = TFFE(!_EQ050, GLOBAL( clk), nreset, VCC, VCC);
_EQ050 = !_LC061 & _X039 & _X040;
_X039 = EXP( nreset & !read & !start & !state~1 & !state~2 & !state~3 &
!state~4 & !stop);
_X040 = EXP(!nreset & !state~4 & state~5);
-- Node name is '|LPM_ADD_SUB:361|addcore:adder|addcore:adder0|gcp2' from file "addcore.tdf" line 160, column 8
-- Equation name is '_LC059', type is buried
_LC059 = LCELL( _EQ051 $ idcnt2);
_EQ051 = idcnt1 & !idcnt2;
-- Node name is '|LPM_ADD_SUB:403|addcore:adder|addcore:adder0|gcp2' from file "addcore.tdf" line 160, column 8
-- Equation name is '_LC050', type is buried
_LC050 = LCELL( _EQ052 $ idcnt2);
_EQ052 = idcnt1 & !idcnt2;
-- Node name is '|p2s_altera:shift1~86|74165b:u1|:94' = '|p2s_altera:shift1~86|74165b:u1|Q7'
-- Equation name is '_LC018', type is buried
_LC018 = DFFE( _EQ053 $ GND, GLOBAL( clk), !_EQ054, !_EQ055, VCC);
_EQ053 = iclkih & _LC018
# !iclkih & _LC009;
_EQ054 = !d7 & !istld;
_EQ055 = d7 & !istld;
-- Node name is '|p2s_altera:shift1~86|74165b:u1|:95'
-- Equation name is '_LC009', type is buried
_LC009 = DFFE( _EQ056 $ GND, GLOBAL( clk), !_EQ057, !_EQ058, VCC);
_EQ056 = iclkih & _LC009
# !iclkih & _LC014;
_EQ057 = !d6 & !istld;
_EQ058 = d6 & !istld;
-- Node name is '|p2s_altera:shift1~86|74165b:u1|:96'
-- Equation name is '_LC014', type is buried
_LC014 = DFFE( _EQ059 $ GND, GLOBAL( clk), !_EQ060, !_EQ061, VCC);
_EQ059 = iclkih & _LC014
# !iclkih & _LC013;
_EQ060 = !d5 & !istld;
_EQ061 = d5 & !istld;
-- Node name is '|p2s_altera:shift1~86|74165b:u1|:97'
-- Equation name is '_LC013', type is buried
_LC013 = DFFE( _EQ062 $ GND, GLOBAL( clk), !_EQ063, !_EQ064, VCC);
_EQ062 = iclkih & _LC013
# !iclkih & _LC015;
_EQ063 = !d4 & !istld;
_EQ064 = d4 & !istld;
-- Node name is '|p2s_altera:shift1~86|74165b:u1|:98'
-- Equation name is '_LC015', type is buried
_LC015 = DFFE( _EQ065 $ GND, GLOBAL( clk), !_EQ066, !_EQ067, VCC);
_EQ065 = iclkih & _LC015
# !iclkih & _LC027;
_EQ066 = !d3 & !istld;
_EQ067 = d3 & !istld;
-- Node name is '|p2s_altera:shift1~86|74165b:u1|:99'
-- Equation name is '_LC027', type is buried
_LC027 = DFFE( _EQ068 $ GND, GLOBAL( clk), !_EQ069, !_EQ070, VCC);
_EQ068 = iclkih & _LC027
# !iclkih & _LC031;
_EQ069 = !d2 & !istld;
_EQ070 = d2 & !istld;
-- Node name is '|p2s_altera:shift1~86|74165b:u1|:100'
-- Equation name is '_LC031', type is buried
_LC031 = DFFE( _EQ071 $ GND, GLOBAL( clk), !_EQ072, !_EQ073, VCC);
_EQ071 = iclkih & _LC031
# !iclkih & _LC029;
_EQ072 = !d1 & !istld;
_EQ073 = d1 & !istld;
-- Node name is '|p2s_altera:shift1~86|74165b:u1|:101'
-- Equation name is '_LC029', type is buried
_LC029 = DFFE( _EQ074 $ GND, GLOBAL( clk), !_EQ075, !_EQ076, VCC);
_EQ074 = iclkih & _LC029
# !iclkih & iser;
_EQ075 = !d0 & !istld;
_EQ076 = d0 & !istld;
-- Node name is '~1130~1'
-- Equation name is '~1130~1', location is LC052, type is buried.
-- synthesized logic cell
_LC052 = LCELL( _EQ077 $ GND);
_EQ077 = idcnt2 & read & !state~1 & !state~2 & state~3 & !state~4 &
!state~5 & !stop
# idcnt2 & !state~1 & !state~2 & state~3 & !state~4 & !state~5 &
!stop & write
# idcnt2 & !start & !state~1 & !state~2 & !state~3 & !state~4 &
!state~5 & !stop
# !idcnt0 & !idcnt1 & state~1 & !state~2 & state~3 & !state~4 &
state~5
# !idcnt0 & !idcnt1 & !state~1 & !state~2 & state~3 & state~4 &
!state~5;
-- Node name is '~1202~1'
-- Equation name is '~1202~1', location is LC042, type is buried.
-- synthesized logic cell
_LC042 = LCELL( _EQ078 $ GND);
_EQ078 = idcnt1 & read & !state~1 & !state~2 & state~3 & !state~4 &
!state~5 & !stop
# idcnt1 & !state~1 & !state~2 & state~3 & !state~4 & !state~5 &
!stop & write
# idcnt1 & !start & !state~1 & !state~2 & !state~3 & !state~4 &
!state~5 & !stop
# idcnt1 & state~1 & state~2 & !state~3 & state~4 & !state~5
# !idcnt0 & state~1 & !state~2 & state~3 & !state~4 & state~5;
-- Node name is '~1274~1'
-- Equation name is '~1274~1', location is LC041, type is buried.
-- synthesized logic cell
_LC041 = LCELL( _EQ079 $ GND);
_EQ079 = state~1 & !state~2 & state~3 & !state~4 & state~5
# !state~1 & !state~2 & state~3 & state~4 & !state~5
# idcnt0 & !start & !state~1 & !state~2 & !state~3 & !state~4 &
!state~5 & !stop
# idcnt0 & read & !state~1 & !state~2 & state~3 & !state~5 &
!stop
# idcnt0 & !state~1 & !state~2 & state~3 & !state~5 & !stop &
write;
-- Shareable expanders that are duplicated in multiple LABs:
-- _X001 occurs in LABs A, B
Project Information d:\vhdl\i2c\i2c1.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = on
Rules = EPLD Rules
Logic Synthesis:
Synthesis Type Used = Standard
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'MAX7000S' family
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
PARALLEL_EXPANDERS = off
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SOFT_BUFFER_INSERTION = on
SUBFACTOR_EXTRACTION = on
TURBO_BIT = on
XOR_SYNTHESIS = on
IGNORE_SOFT_BUFFERS = off
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
One-Hot State Machine Encoding = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Use Quartus Fitter = off
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:03
Database Builder 00:00:01
Logic Synthesizer 00:00:03
Partitioner 00:00:00
Fitter 00:00:01
Timing SNF Extractor 00:00:00
Assembler 00:00:04
Design Doctor 00:00:08
-------------------------- --------
Total Time 00:00:20
Memory Allocated
-----------------
Peak memory allocated during compilation = 11,533K
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