📄 i2c1.rpt
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| | | | | | | | | | +----------- LC47 dcnt0
| | | | | | | | | | | +--------- LC34 ishift
| | | | | | | | | | | | +------- LC39 idcnt1
| | | | | | | | | | | | | +----- LC37 idcnt0
| | | | | | | | | | | | | | +--- LC42 ~1202~1
| | | | | | | | | | | | | | | +- LC41 ~1274~1
| | | | | | | | | | | | | | | |
| | | | | | | | | | | | | | | | Other LABs fed by signals
| | | | | | | | | | | | | | | | that feed LAB 'C'
LC | | | | | | | | | | | | | | | | | A B C D | Logic cells that feed LAB 'C':
LC43 -> - - - * - - - - - - - - - - - - | - - * - | <-- state~1~1
LC36 -> - - * * * * - * * - - * * * * * | - * * * | <-- state~1
LC45 -> - - - - - - * - - - - - - - - - | - - * - | <-- state~3~1
LC38 -> - - * * * * * * * - - * * * * * | - * * * | <-- state~3
LC44 -> - - * * * * * * * - - * * * * * | - * * * | <-- state~4
LC35 -> - - * * * * - * * - - * * * * * | - * * * | <-- state~5
LC34 -> - - - - - - - - - - - * - - - - | * * * - | <-- ishift
LC39 -> - - - - - - - - - * - - * - * - | - - * * | <-- idcnt1
LC37 -> - - - - - - - - - - * - * * * * | - - * * | <-- idcnt0
LC42 -> - - - - - - - - - - - - * - - - | - - * - | <-- ~1202~1
LC41 -> - - - - - - - - - - - - - * - - | - - * - | <-- ~1274~1
Pin
43 -> - - - - - - - - - - - - - - - - | - - - - | <-- clk
5 -> * * - * - * * * * * * * * * - - | - * * * | <-- nreset
17 -> - - - * - * - * * - - * - - * * | - - * * | <-- read
25 -> - - * - - * - - * - - * - - * * | - - * * | <-- start
18 -> - - - * - * - * * - - * - - * * | - - * * | <-- stop
16 -> - - - * - * - - - - - * - - * * | - - * * | <-- write
LC49 -> - - * * * * - * * - - * * * * * | - * * * | <-- state~2
LC51 -> - - - - - - - * - - - - - - - - | - - * - | <-- state~4~1
LC61 -> - - - - - - - - * - - - - - - - | - - * - | <-- state~5~1
LC32 -> * - - - - - - - - - - - - - - - | - - * - | <-- sclo
LC30 -> - * - - - - - - - - - - - - - - | - - * - | <-- sdao
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).
Device-Specific Information: d:\vhdl\i2c\i2c1.rpt
i2c1
** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'D':
Logic cells placed in LAB 'D'
+------------------------------- LC59 |LPM_ADD_SUB:361|addcore:adder|addcore:adder0|gcp2
| +----------------------------- LC50 |LPM_ADD_SUB:403|addcore:adder|addcore:adder0|gcp2
| | +--------------------------- LC49 state~2
| | | +------------------------- LC51 state~4~1
| | | | +----------------------- LC61 state~5~1
| | | | | +--------------------- LC57 iclkih
| | | | | | +------------------- LC58 istld
| | | | | | | +----------------- LC54 iser
| | | | | | | | +--------------- LC55 dcnt3
| | | | | | | | | +------------- LC63 dcnt2
| | | | | | | | | | +----------- LC64 iflag
| | | | | | | | | | | +--------- LC62 shift_state1
| | | | | | | | | | | | +------- LC56 shift_state0
| | | | | | | | | | | | | +----- LC60 idcnt3
| | | | | | | | | | | | | | +--- LC53 idcnt2
| | | | | | | | | | | | | | | +- LC52 ~1130~1
| | | | | | | | | | | | | | | |
| | | | | | | | | | | | | | | | Other LABs fed by signals
| | | | | | | | | | | | | | | | that feed LAB 'D'
LC | | | | | | | | | | | | | | | | | A B C D | Logic cells that feed LAB 'D':
LC59 -> - - - - - - - - - - - - - * - - | - - - * | <-- |LPM_ADD_SUB:361|addcore:adder|addcore:adder0|gcp2
LC50 -> - - - - - - - - - - - - - * - - | - - - * | <-- |LPM_ADD_SUB:403|addcore:adder|addcore:adder0|gcp2
LC49 -> - - * * * - - - - - * - - * * * | - * * * | <-- state~2
LC55 -> - - - - - - - - - - - - * - - - | - - - * | <-- dcnt3
LC63 -> - - - - - - - - - - - * * - - - | - - - * | <-- dcnt2
LC64 -> - - - - - - - - - - * * * - - - | - - - * | <-- iflag
LC62 -> - - - - - * * * - - - * * - - - | - - - * | <-- shift_state1
LC56 -> - - - - - * * * - - - * * - - - | - - - * | <-- shift_state0
LC60 -> - - * * * - - - * - * - - * - - | - - - * | <-- idcnt3
LC53 -> * * * * * - - - - * * - - - * * | - - - * | <-- idcnt2
LC52 -> - - - - - - - - - - - - - - * - | - - - * | <-- ~1130~1
Pin
43 -> - - - - - - - - - - - - - - - - | - - - - | <-- clk
5 -> - - * * * - - - * * * - - * * - | - * * * | <-- nreset
17 -> - - * * * - - - - - - - - * - * | - - * * | <-- read
25 -> - - - * - - - - - - - - - * - * | - - * * | <-- start
18 -> - - * * * - - - - - - - - * - * | - - * * | <-- stop
16 -> - - * * * - - - - - - - - * - * | - - * * | <-- write
LC36 -> - - * * * - - - - - * - - * * * | - * * * | <-- state~1
LC46 -> - - * - - - - - - - - - - - - - | - - - * | <-- state~2~1
LC38 -> - - * * * - - - - - * - - * * * | - * * * | <-- state~3
LC44 -> - - * * * - - - - - * - - * * * | - * * * | <-- state~4
LC35 -> - - * * * - - - - - * - - * * * | - * * * | <-- state~5
LC48 -> - - - - - - - - - - - * * - - - | - - - * | <-- dcnt1
LC47 -> - - - - - - - - - - - * * - - - | - - - * | <-- dcnt0
LC39 -> * * * * * - - - - - * - - - - * | - - * * | <-- idcnt1
LC37 -> - - * * * - - - - - * - - * - * | - - * * | <-- idcnt0
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).
Device-Specific Information: d:\vhdl\i2c\i2c1.rpt
i2c1
** EQUATIONS **
clk : INPUT;
nreset : INPUT;
read : INPUT;
start : INPUT;
stop : INPUT;
write : INPUT;
-- Node name is ':35' = 'dcnt0'
-- Equation name is 'dcnt0', location is LC047, type is buried.
dcnt0 = DFFE( idcnt0 $ GND, GLOBAL( clk), nreset, VCC, VCC);
-- Node name is ':34' = 'dcnt1'
-- Equation name is 'dcnt1', location is LC048, type is buried.
dcnt1 = DFFE( idcnt1 $ GND, GLOBAL( clk), nreset, VCC, VCC);
-- Node name is ':33' = 'dcnt2'
-- Equation name is 'dcnt2', location is LC063, type is buried.
dcnt2 = DFFE( idcnt2 $ GND, GLOBAL( clk), nreset, VCC, VCC);
-- Node name is ':32' = 'dcnt3'
-- Equation name is 'dcnt3', location is LC055, type is buried.
dcnt3 = DFFE( idcnt3 $ GND, GLOBAL( clk), VCC, nreset, VCC);
-- Node name is 'd0' = ':17'
-- Equation name is 'd0', type is bidir
d0 = TRI(_LC019, VCC);
_LC019 = DFFE( _EQ001 $ d0, GLOBAL( clk), VCC, VCC, VCC);
_EQ001 = !d0 & ishift & shift0 & state_s2p3 & _X001
# d0 & ishift & !shift0 & state_s2p3 & _X001;
_X001 = EXP(!state_s2p0 & !state_s2p1 & !state_s2p2);
-- Node name is 'd1' = ':15'
-- Equation name is 'd1', type is bidir
d1 = TRI(_LC020, VCC);
_LC020 = DFFE( _EQ002 $ d1, GLOBAL( clk), VCC, VCC, VCC);
_EQ002 = !d1 & ishift & shift1 & state_s2p3 & _X001
# d1 & ishift & !shift1 & state_s2p3 & _X001;
_X001 = EXP(!state_s2p0 & !state_s2p1 & !state_s2p2);
-- Node name is 'd2' = ':13'
-- Equation name is 'd2', type is bidir
d2 = TRI(_LC017, VCC);
_LC017 = DFFE( _EQ003 $ d2, GLOBAL( clk), VCC, VCC, VCC);
_EQ003 = !d2 & ishift & shift2 & state_s2p3 & _X001
# d2 & ishift & !shift2 & state_s2p3 & _X001;
_X001 = EXP(!state_s2p0 & !state_s2p1 & !state_s2p2);
-- Node name is 'd3' = ':11'
-- Equation name is 'd3', type is bidir
d3 = TRI(_LC011, VCC);
_LC011 = DFFE( _EQ004 $ d3, GLOBAL( clk), VCC, VCC, VCC);
_EQ004 = !d3 & ishift & shift3 & state_s2p3 & _X001
# d3 & ishift & !shift3 & state_s2p3 & _X001;
_X001 = EXP(!state_s2p0 & !state_s2p1 & !state_s2p2);
-- Node name is 'd4' = ':9'
-- Equation name is 'd4', type is bidir
d4 = TRI(_LC005, VCC);
_LC005 = DFFE( _EQ005 $ d4, GLOBAL( clk), VCC, VCC, VCC);
_EQ005 = !d4 & ishift & shift4 & state_s2p3 & _X001
# d4 & ishift & !shift4 & state_s2p3 & _X001;
_X001 = EXP(!state_s2p0 & !state_s2p1 & !state_s2p2);
-- Node name is 'd5' = ':7'
-- Equation name is 'd5', type is bidir
d5 = TRI(_LC004, VCC);
_LC004 = DFFE( _EQ006 $ d5, GLOBAL( clk), VCC, VCC, VCC);
_EQ006 = !d5 & ishift & shift5 & state_s2p3 & _X001
# d5 & ishift & !shift5 & state_s2p3 & _X001;
_X001 = EXP(!state_s2p0 & !state_s2p1 & !state_s2p2);
-- Node name is 'd6' = ':5'
-- Equation name is 'd6', type is bidir
d6 = TRI(_LC003, VCC);
_LC003 = DFFE( _EQ007 $ d6, GLOBAL( clk), VCC, VCC, VCC);
_EQ007 = !d6 & ishift & shift6 & state_s2p3 & _X001
# d6 & ishift & !shift6 & state_s2p3 & _X001;
_X001 = EXP(!state_s2p0 & !state_s2p1 & !state_s2p2);
-- Node name is 'd7' = ':3'
-- Equation name is 'd7', type is bidir
d7 = TRI(_LC001, VCC);
_LC001 = DFFE( _EQ008 $ d7, GLOBAL( clk), VCC, VCC, VCC);
_EQ008 = !d7 & ishift & shift7 & state_s2p3 & _X001
# d7 & ishift & !shift7 & state_s2p3 & _X001;
_X001 = EXP(!state_s2p0 & !state_s2p1 & !state_s2p2);
-- Node name is ':27' = 'iclkih'
-- Equation name is 'iclkih', location is LC057, type is buried.
iclkih = DFFE( _EQ009 $ GND, GLOBAL( clk), VCC, VCC, VCC);
_EQ009 = shift_state0 & !shift_state1;
-- Node name is ':112' = 'idcnt0'
-- Equation name is 'idcnt0', location is LC037, type is buried.
idcnt0 = TFFE(!_EQ010, GLOBAL( clk), VCC, VCC, nreset);
_EQ010 = !_LC041 & _X002;
_X002 = EXP( idcnt0 & state~1 & state~2 & !state~3 & state~4 & !state~5);
-- Node name is ':111' = 'idcnt1'
-- Equation name is 'idcnt1', location is LC039, type is buried.
idcnt1 = TFFE(!_EQ011, GLOBAL( clk), VCC, VCC, nreset);
_EQ011 = !_LC042 & _X003;
_X003 = EXP(!idcnt0 & !state~1 & !state~2 & state~3 & state~4 & !state~5);
-- Node name is ':110' = 'idcnt2'
-- Equation name is 'idcnt2', location is LC053, type is buried.
idcnt2 = TFFE(!_EQ012, GLOBAL( clk), VCC, VCC, nreset);
_EQ012 = !_LC052 & _X004;
_X004 = EXP( idcnt2 & state~1 & state~2 & !state~3 & state~4 & !state~5);
-- Node name is ':109' = 'idcnt3'
-- Equation name is 'idcnt3', location is LC060, type is buried.
idcnt3 = TFFE(!_EQ013, GLOBAL( clk), VCC, VCC, nreset);
_EQ013 = _X005 & _X006 & _X007 & _X008 & _X009 & _X010;
_X005 = EXP(!idcnt3 & !state~1 & !state~2 & state~3 & !state~4 & !state~5 &
!stop & write);
_X006 = EXP(!idcnt3 & read & !state~1 & !state~2 & state~3 & !state~4 &
!state~5 & !stop);
_X007 = EXP(!idcnt3 & !start & !state~1 & !state~2 & !state~3 & !state~4 &
!state~5 & !stop);
_X008 = EXP(!idcnt0 & !_LC050 & state~1 & !state~2 & state~3 & !state~4 &
state~5);
_X009 = EXP(!idcnt0 & !_LC059 & !state~1 & !state~2 & state~3 & state~4 &
!state~5);
_X010 = EXP(!idcnt3 & state~1 & state~2 & !state~3 & state~4 & !state~5);
-- Node name is ':40' = 'iflag'
-- Equation name is 'iflag', location is LC064, type is buried.
iflag = DFFE( _EQ014 $ _EQ015, GLOBAL( clk), VCC, VCC, nreset);
_EQ014 = iflag & state~4
# iflag & !state~5
# iflag & !state~3;
_EQ015 = state~1 & !state~2 & state~3 & !state~4 & state~5 & _X011;
_X011 = EXP( idcnt0 & !idcnt1 & !idcnt2 & !idcnt3);
-- Node name is ':107' = 'iscl'
-- Equation name is 'iscl', location is LC021, type is buried.
iscl = DFFE( _EQ016 $ _EQ017, GLOBAL( clk), VCC, VCC, nreset);
_EQ016 = state~1 & state~2 & state~4 & !state~5 & _X012 & _X013 &
_X014 & _X015 & _X016
# state~2 & !state~3 & state~4 & !state~5 & _X012 & _X013 &
_X014 & _X015 & _X016
# state~1 & !state~2 & state~3 & !state~4 & _X012 & _X013 &
_X014 & _X015 & _X016;
_X012 = EXP(!iscl & !state~2 & !state~3 & state~5);
_X013 = EXP(!state~1 & !state~2 & state~3 & !state~5);
_X014 = EXP(!state~1 & !state~3 & !state~4 & !state~5);
_X015 = EXP( state~1 & !state~4 & state~5);
_X016 = EXP(!iscl & state~4 & state~5);
_EQ017 = _X012 & _X013 & _X014 & _X015 & _X016;
_X012 = EXP(!iscl & !state~2 & !state~3 & state~5);
_X013 = EXP(!state~1 & !state~2 & state~3 & !state~5);
_X014 = EXP(!state~1 & !state~3 & !state~4 & !state~5);
_X015 = EXP( state~1 & !state~4 & state~5);
_X016 = EXP(!iscl & state~4 & state~5);
-- Node name is ':108' = 'isda'
-- Equation name is 'isda', location is LC024, type is buried.
isda = DFFE( _EQ018 $ !state~5, GLOBAL( clk), VCC, VCC, nreset);
_EQ018 = _X017 & _X018 & _X019 & _X020 & _X021;
_X017 = EXP(!state~1 & state~2 & !state~3 & state~4 & !state~5);
_X018 = EXP( state~1 & !state~2 & !state~3 & !state~5);
_X019 = EXP( isda & !state~1 & state~2 & state~3 & !state~4 & !state~5);
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