📄 i2c1.rpt
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24 33 C BIDIR 0 0 0 1 1 0 1 SDA
25 (35) (C) INPUT 0 0 0 0 0 0 9 start
18 (21) (B) INPUT 0 0 0 0 0 0 12 stop
16 (25) (B) INPUT 0 0 0 0 0 0 10 write
Code:
s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
G = Global Source. Fan-out destinations counted here do not include destinations
that are driven using global routing resources. Refer to the Auto Global Signals,
Clock Signals, Clear Signals, Synchronous Load Signals, and Synchronous Clear Signals
Sections of this Report File for information on which signals' fan-outs are used as
Clock, Clear, Preset, Output Enable, and synchronous Load signals.
Device-Specific Information: d:\vhdl\i2c\i2c1.rpt
i2c1
** OUTPUTS **
Shareable
Expanders Fan-In Fan-Out
Pin LC LAB Primitive Code Total Shared n/a INP FBK OUT FBK Name
20 19 B TRI/FF + t 1 1 0 0 7 1 1 d0
19 20 B TRI/FF + t 1 1 0 0 7 1 1 d1
21 17 B TRI/FF + t 1 1 0 0 7 1 1 d2
6 11 A TRI/FF + t 1 1 0 0 7 1 1 d3
8 5 A TRI/FF + t 1 1 0 0 7 1 1 d4
9 4 A TRI/FF + t 1 1 0 0 7 1 1 d5
11 3 A TRI/FF + t 1 1 0 0 7 1 1 d6
12 1 A TRI/FF + t 1 1 0 0 7 1 1 d7
28 40 C TRI/FF + t 0 0 0 1 1 0 0 SCL
24 33 C TRI/FF + t 0 0 0 1 1 0 1 SDA
Code:
s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
Device-Specific Information: d:\vhdl\i2c\i2c1.rpt
i2c1
** BURIED LOGIC **
Shareable
Expanders Fan-In Fan-Out
Pin LC LAB Primitive Code Total Shared n/a INP FBK OUT FBK Name
- 59 D SOFT t 0 0 0 0 2 0 1 |LPM_ADD_SUB:361|addcore:adder|addcore:adder0|gcp2
- 50 D SOFT t 0 0 0 0 2 0 1 |LPM_ADD_SUB:403|addcore:adder|addcore:adder0|gcp2
- 18 B DFFE + t 0 0 0 0 5 0 3 |p2s_altera:shift1~86|74165b:u1|Q7 (|p2s_altera:shift1~86|74165b:u1|:94)
- 9 A DFFE + t 0 0 0 0 5 0 2 |p2s_altera:shift1~86|74165b:u1|:95
(5) 14 A DFFE + t 0 0 0 0 5 0 2 |p2s_altera:shift1~86|74165b:u1|:96
- 13 A DFFE + t 0 0 0 0 5 0 2 |p2s_altera:shift1~86|74165b:u1|:97
- 15 A DFFE + t 0 0 0 0 5 0 2 |p2s_altera:shift1~86|74165b:u1|:98
- 27 B DFFE + t 0 0 0 0 5 0 2 |p2s_altera:shift1~86|74165b:u1|:99
- 31 B DFFE + t 0 0 0 0 5 0 2 |p2s_altera:shift1~86|74165b:u1|:100
- 29 B DFFE + t 0 0 0 0 5 0 2 |p2s_altera:shift1~86|74165b:u1|:101
- 43 C SOFT s t 1 0 1 1 5 0 1 state~1~1
(26) 36 C DFFE + t 4 0 1 4 6 0 22 state~1
(31) 46 C SOFT s t 1 0 1 0 5 0 1 state~2~1
(33) 49 D DFFE + t 4 0 1 4 10 0 22 state~2
- 45 C SOFT s t 1 0 1 5 5 0 1 state~3~1
- 38 C TFFE + t 1 0 0 1 3 0 23 state~3
(34) 51 D SOFT s t 1 0 1 5 9 0 1 state~4~1
- 44 C TFFE + t 2 0 0 3 6 0 23 state~4
- 61 D SOFT s t 1 0 1 4 9 0 1 state~5~1
(25) 35 C TFFE + t 2 0 0 4 6 0 22 state~5
(39) 57 D DFFE + t 0 0 0 0 2 0 8 iclkih (:27)
- 58 D DFFE + t 0 0 0 0 2 0 8 istld (:28)
- 54 D DFFE + t 0 0 0 0 2 0 1 iser (:29)
- 55 D DFFE + t 0 0 0 1 1 0 1 dcnt3 (:32)
- 63 D DFFE + t 0 0 0 1 1 0 2 dcnt2 (:33)
(32) 48 C DFFE + t 0 0 0 1 1 0 2 dcnt1 (:34)
- 47 C DFFE + t 0 0 0 1 1 0 2 dcnt0 (:35)
(13) 32 B DFFE + t 6 5 1 1 6 1 0 sclo (:36)
(14) 30 B DFFE + t 5 5 0 1 7 1 0 sdao (:37)
- 34 C TFFE + t 0 0 0 5 6 8 13 ishift (:38)
(41) 64 D DFFE + t 2 0 1 1 10 0 3 iflag (:40)
(40) 62 D TFFE + t 0 0 0 0 6 0 5 shift_state1 (:41)
(38) 56 D DFFE + t 0 0 0 0 7 0 5 shift_state0 (:42)
- 26 B DFFE + t 0 0 0 1 5 8 12 state_s2p3 (:43)
(16) 25 B TFFE + t 0 0 0 1 5 8 10 state_s2p2 (:44)
- 23 B DFFE + t 0 0 0 1 4 8 11 state_s2p1 (:45)
- 22 B DFFE + t 0 0 0 1 3 8 12 state_s2p0 (:46)
- 12 A DFFE + t 3 1 1 0 7 1 2 shift7 (:47)
(7) 8 A DFFE + t 3 1 1 0 7 1 2 shift6 (:48)
- 6 A DFFE + t 3 1 1 0 7 1 2 shift5 (:49)
(4) 16 A DFFE + t 3 1 1 0 7 1 2 shift4 (:50)
- 10 A DFFE + t 3 1 1 0 7 1 2 shift3 (:51)
- 7 A DFFE + t 3 1 1 0 7 1 2 shift2 (:52)
- 2 A DFFE + t 3 1 1 0 7 1 2 shift1 (:53)
- 28 B DFFE + t 3 1 1 0 7 1 1 shift0 (:54)
(18) 21 B DFFE + t 6 5 1 1 6 0 2 iscl (:107)
(17) 24 B DFFE + t 5 5 0 1 7 0 2 isda (:108)
- 60 D TFFE + t 6 0 0 5 9 0 6 idcnt3 (:109)
(37) 53 D TFFE + t 1 0 0 1 7 0 9 idcnt2 (:110)
- 39 C TFFE + t 1 0 0 1 7 0 9 idcnt1 (:111)
(27) 37 C TFFE + t 1 0 0 1 7 0 11 idcnt0 (:112)
(36) 52 D SOFT s t 1 0 1 4 8 0 1 ~1130~1
- 42 C SOFT s t 1 0 1 4 7 0 1 ~1202~1
(29) 41 C SOFT s t 1 0 1 4 6 0 1 ~1274~1
Code:
s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
Device-Specific Information: d:\vhdl\i2c\i2c1.rpt
i2c1
** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'A':
Logic cells placed in LAB 'A'
+------------------------------- LC11 d3
| +----------------------------- LC5 d4
| | +--------------------------- LC4 d5
| | | +------------------------- LC3 d6
| | | | +----------------------- LC1 d7
| | | | | +--------------------- LC9 |p2s_altera:shift1~86|74165b:u1|:95
| | | | | | +------------------- LC14 |p2s_altera:shift1~86|74165b:u1|:96
| | | | | | | +----------------- LC13 |p2s_altera:shift1~86|74165b:u1|:97
| | | | | | | | +--------------- LC15 |p2s_altera:shift1~86|74165b:u1|:98
| | | | | | | | | +------------- LC12 shift7
| | | | | | | | | | +----------- LC8 shift6
| | | | | | | | | | | +--------- LC6 shift5
| | | | | | | | | | | | +------- LC16 shift4
| | | | | | | | | | | | | +----- LC10 shift3
| | | | | | | | | | | | | | +--- LC7 shift2
| | | | | | | | | | | | | | | +- LC2 shift1
| | | | | | | | | | | | | | | |
| | | | | | | | | | | | | | | | Other LABs fed by signals
| | | | | | | | | | | | | | | | that feed LAB 'A'
LC | | | | | | | | | | | | | | | | | A B C D | Logic cells that feed LAB 'A':
LC11 -> * - - - - - - - * - - - - - - - | * - - - | <-- d3
LC5 -> - * - - - - - * - - - - - - - - | * - - - | <-- d4
LC4 -> - - * - - - * - - - - - - - - - | * - - - | <-- d5
LC3 -> - - - * - * - - - - - - - - - - | * - - - | <-- d6
LC1 -> - - - - * - - - - - - - - - - - | * * - - | <-- d7
LC9 -> - - - - - * - - - - - - - - - - | * * - - | <-- |p2s_altera:shift1~86|74165b:u1|:95
LC14 -> - - - - - * * - - - - - - - - - | * - - - | <-- |p2s_altera:shift1~86|74165b:u1|:96
LC13 -> - - - - - - * * - - - - - - - - | * - - - | <-- |p2s_altera:shift1~86|74165b:u1|:97
LC15 -> - - - - - - - * * - - - - - - - | * - - - | <-- |p2s_altera:shift1~86|74165b:u1|:98
LC12 -> - - - - * - - - - * * - - - - - | * - - - | <-- shift7
LC8 -> - - - * - - - - - - * * - - - - | * - - - | <-- shift6
LC6 -> - - * - - - - - - - - * * - - - | * - - - | <-- shift5
LC16 -> - * - - - - - - - - - - * * - - | * - - - | <-- shift4
LC10 -> * - - - - - - - - - - - - * * - | * - - - | <-- shift3
LC7 -> - - - - - - - - - - - - - - * * | * * - - | <-- shift2
LC2 -> - - - - - - - - - - - - - - - * | * * - - | <-- shift1
Pin
43 -> - - - - - - - - - - - - - - - - | - - - - | <-- clk
LC27 -> - - - - - - - - * - - - - - - - | * * - - | <-- |p2s_altera:shift1~86|74165b:u1|:99
LC33 -> - - - - - - - - - * - - - - - - | * - - - | <-- SDA
LC57 -> - - - - - * * * * - - - - - - - | * * - - | <-- iclkih
LC58 -> - - - - - * * * * - - - - - - - | * * - - | <-- istld
LC34 -> * * * * * - - - - * * * * * * * | * * * - | <-- ishift
LC26 -> * * * * * - - - - * * * * * * * | * * - - | <-- state_s2p3
LC25 -> * * * * * - - - - * * * * * * * | * * - - | <-- state_s2p2
LC23 -> * * * * * - - - - * * * * * * * | * * - - | <-- state_s2p1
LC22 -> * * * * * - - - - * * * * * * * | * * - - | <-- state_s2p0
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).
Device-Specific Information: d:\vhdl\i2c\i2c1.rpt
i2c1
** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'B':
Logic cells placed in LAB 'B'
+------------------------------- LC19 d0
| +----------------------------- LC20 d1
| | +--------------------------- LC17 d2
| | | +------------------------- LC18 |p2s_altera:shift1~86|74165b:u1|Q7
| | | | +----------------------- LC27 |p2s_altera:shift1~86|74165b:u1|:99
| | | | | +--------------------- LC31 |p2s_altera:shift1~86|74165b:u1|:100
| | | | | | +------------------- LC29 |p2s_altera:shift1~86|74165b:u1|:101
| | | | | | | +----------------- LC32 sclo
| | | | | | | | +--------------- LC30 sdao
| | | | | | | | | +------------- LC26 state_s2p3
| | | | | | | | | | +----------- LC25 state_s2p2
| | | | | | | | | | | +--------- LC23 state_s2p1
| | | | | | | | | | | | +------- LC22 state_s2p0
| | | | | | | | | | | | | +----- LC28 shift0
| | | | | | | | | | | | | | +--- LC21 iscl
| | | | | | | | | | | | | | | +- LC24 isda
| | | | | | | | | | | | | | | |
| | | | | | | | | | | | | | | | Other LABs fed by signals
| | | | | | | | | | | | | | | | that feed LAB 'B'
LC | | | | | | | | | | | | | | | | | A B C D | Logic cells that feed LAB 'B':
LC19 -> * - - - - - * - - - - - - - - - | - * - - | <-- d0
LC20 -> - * - - - * - - - - - - - - - - | - * - - | <-- d1
LC17 -> - - * - * - - - - - - - - - - - | - * - - | <-- d2
LC18 -> - - - * - - - - * - - - - - - * | - * - - | <-- |p2s_altera:shift1~86|74165b:u1|Q7
LC27 -> - - - - * - - - - - - - - - - - | * * - - | <-- |p2s_altera:shift1~86|74165b:u1|:99
LC31 -> - - - - * * - - - - - - - - - - | - * - - | <-- |p2s_altera:shift1~86|74165b:u1|:100
LC29 -> - - - - - * * - - - - - - - - - | - * - - | <-- |p2s_altera:shift1~86|74165b:u1|:101
LC26 -> * * * - - - - - - * * * * * - - | * * - - | <-- state_s2p3
LC25 -> * * * - - - - - - * * - - * - - | * * - - | <-- state_s2p2
LC23 -> * * * - - - - - - * * * - * - - | * * - - | <-- state_s2p1
LC22 -> * * * - - - - - - * * * * * - - | * * - - | <-- state_s2p0
LC28 -> * - - - - - - - - - - - - * - - | - * - - | <-- shift0
LC21 -> - - - - - - - * - - - - - - * - | - * - - | <-- iscl
LC24 -> - - - - - - - - * - - - - - - * | - * - - | <-- isda
Pin
43 -> - - - - - - - - - - - - - - - - | - - - - | <-- clk
5 -> - - - - - - - * * * * * * - * * | - * * * | <-- nreset
LC1 -> - - - * - - - - - - - - - - - - | * * - - | <-- d7
LC9 -> - - - * - - - - - - - - - - - - | * * - - | <-- |p2s_altera:shift1~86|74165b:u1|:95
LC36 -> - - - - - - - * * - - - - - * * | - * * * | <-- state~1
LC49 -> - - - - - - - * * - - - - - * * | - * * * | <-- state~2
LC38 -> - - - - - - - * * - - - - - * * | - * * * | <-- state~3
LC44 -> - - - - - - - * * - - - - - * * | - * * * | <-- state~4
LC35 -> - - - - - - - * * - - - - - * * | - * * * | <-- state~5
LC57 -> - - - * * * * - - - - - - - - - | * * - - | <-- iclkih
LC58 -> - - - * * * * - - - - - - - - - | * * - - | <-- istld
LC54 -> - - - - - - * - - - - - - - - - | - * - - | <-- iser
LC34 -> * * * - - - - - - * * * * * - - | * * * - | <-- ishift
LC7 -> - - * - - - - - - - - - - - - - | * * - - | <-- shift2
LC2 -> - * - - - - - - - - - - - * - - | * * - - | <-- shift1
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).
Device-Specific Information: d:\vhdl\i2c\i2c1.rpt
i2c1
** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'C':
Logic cells placed in LAB 'C'
+------------------------------- LC40 SCL
| +----------------------------- LC33 SDA
| | +--------------------------- LC43 state~1~1
| | | +------------------------- LC36 state~1
| | | | +----------------------- LC46 state~2~1
| | | | | +--------------------- LC45 state~3~1
| | | | | | +------------------- LC38 state~3
| | | | | | | +----------------- LC44 state~4
| | | | | | | | +--------------- LC35 state~5
| | | | | | | | | +------------- LC48 dcnt1
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