📄 i2c1.rpt
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Project Information d:\vhdl\i2c\i2c1.rpt
MAX+plus II Compiler Report File
Version 9.5 2/8/2000
Compiled: 05/10/2003 13:11:16
Copyright (C) 1988-2000 Altera Corporation
Any megafunction design, and related net list (encrypted or decrypted),
support information, device programming or simulation file, and any other
associated documentation or information provided by Altera or a partner
under Altera's Megafunction Partnership Program may be used only to
program PLD devices (but not masked PLD devices) from Altera. Any other
use of such megafunction design, net list, support information, device
programming or simulation file, or any other related documentation or
information is prohibited for any other purpose, including, but not
limited to modification, reverse engineering, de-compiling, or use with
any other silicon devices, unless such use is explicitly licensed under
a separate agreement with Altera or a megafunction partner. Title to
the intellectual property, including patents, copyrights, trademarks,
trade secrets, or maskworks, embodied in any such megafunction design,
net list, support information, device programming or simulation file, or
any other related documentation or information provided by Altera or a
megafunction partner, remains with Altera, the megafunction partner, or
their respective licensors. No other licenses, including any licenses
needed under any third party's intellectual property, are provided herein.
***** Project compilation was successful
I2C1
** DEVICE SUMMARY **
Chip/ Input Output Bidir Shareable
POF Device Pins Pins Pins LCs Expanders % Utilized
i2c1 EPM7064SLC44-5 6 0 10 64 41 100%
User Pins: 6 0 10
Project Information d:\vhdl\i2c\i2c1.rpt
** PROJECT COMPILATION MESSAGES **
Design Doctor Warning: Complex combinatorial logic drives Reset node (ID '|p2s_altera:shift1~86|74165b:u1|:102') -- Reset should be driven by a pin or a single logic primitive
Design Doctor Warning: Complex combinatorial logic drives Reset node (ID '|p2s_altera:shift1~86|74165b:u1|:105') -- Reset should be driven by a pin or a single logic primitive
Design Doctor Warning: Complex combinatorial logic drives Reset node (ID '|p2s_altera:shift1~86|74165b:u1|:106') -- Reset should be driven by a pin or a single logic primitive
Design Doctor Warning: Complex combinatorial logic drives Reset node (ID '|p2s_altera:shift1~86|74165b:u1|:109') -- Reset should be driven by a pin or a single logic primitive
Design Doctor Warning: Complex combinatorial logic drives Reset node (ID '|p2s_altera:shift1~86|74165b:u1|:110') -- Reset should be driven by a pin or a single logic primitive
Design Doctor Warning: Complex combinatorial logic drives Reset node (ID '|p2s_altera:shift1~86|74165b:u1|:113') -- Reset should be driven by a pin or a single logic primitive
Design Doctor Warning: Complex combinatorial logic drives Reset node (ID '|p2s_altera:shift1~86|74165b:u1|:114') -- Reset should be driven by a pin or a single logic primitive
Design Doctor Warning: Complex combinatorial logic drives Reset node (ID '|p2s_altera:shift1~86|74165b:u1|:116') -- Reset should be driven by a pin or a single logic primitive
Design Doctor Warning: Multiple flipflops and/or synchronous memories drive Preset node (ID '|p2s_altera:shift1~86|74165b:u1|:103')
Design Doctor Warning: Multiple flipflops and/or synchronous memories drive Preset node (ID '|p2s_altera:shift1~86|74165b:u1|:104')
Design Doctor Warning: Multiple flipflops and/or synchronous memories drive Preset node (ID '|p2s_altera:shift1~86|74165b:u1|:107')
Design Doctor Warning: Multiple flipflops and/or synchronous memories drive Preset node (ID '|p2s_altera:shift1~86|74165b:u1|:108')
Design Doctor Warning: Multiple flipflops and/or synchronous memories drive Preset node (ID '|p2s_altera:shift1~86|74165b:u1|:111')
Design Doctor Warning: Multiple flipflops and/or synchronous memories drive Preset node (ID '|p2s_altera:shift1~86|74165b:u1|:112')
Design Doctor Warning: Multiple flipflops and/or synchronous memories drive Preset node (ID '|p2s_altera:shift1~86|74165b:u1|:115')
Design Doctor Warning: Multiple flipflops and/or synchronous memories drive Preset node (ID '|p2s_altera:shift1~86|74165b:u1|:117')
Info: Design Doctor issued 16 warning message(s) with EPLD Rules
Project Information d:\vhdl\i2c\i2c1.rpt
** AUTO GLOBAL SIGNALS **
INFO: Signal 'clk' chosen for auto global Clock
Project Information d:\vhdl\i2c\i2c1.rpt
** STATE MACHINE ASSIGNMENTS **
state: MACHINE
OF BITS (
state~5,
state~4,
state~3,
state~2,
state~1
)
WITH STATES (
idle = B"00000",
start_a = B"01010",
start_b = B"01001",
start_c = B"01000",
start_d = B"01011",
stop_a = B"00010",
stop_b = B"00011",
stop_c = B"00001",
rd_a = B"01111",
rd_b = B"01110",
rd_c = B"01101",
rd_d = B"01100",
wr_a = B"10111",
wr_b = B"10110",
wr_c = B"10100",
wr_d = B"10101",
ack_a = B"00101",
ack_b = B"00111",
ack_c = B"00110",
ack_d = B"00100",
nack_a = B"10011",
nack_b = B"10010",
nack_c = B"10001",
nack_d = B"10000"
);
Project Information d:\vhdl\i2c\i2c1.rpt
** FILE HIERARCHY **
|lpm_add_sub:361|
|lpm_add_sub:361|addcore:adder|
|lpm_add_sub:361|addcore:adder|addcore:adder0|
|lpm_add_sub:361|altshift:result_ext_latency_ffs|
|lpm_add_sub:361|altshift:carry_ext_latency_ffs|
|lpm_add_sub:361|altshift:oflow_ext_latency_ffs|
|lpm_add_sub:403|
|lpm_add_sub:403|addcore:adder|
|lpm_add_sub:403|addcore:adder|addcore:adder0|
|lpm_add_sub:403|altshift:result_ext_latency_ffs|
|lpm_add_sub:403|altshift:carry_ext_latency_ffs|
|lpm_add_sub:403|altshift:oflow_ext_latency_ffs|
|p2s_altera:shift1~86|
|p2s_altera:shift1~86|74165b:u1|
Device-Specific Information: d:\vhdl\i2c\i2c1.rpt
i2c1
***** Logic for device 'i2c1' compiled without errors.
Device: EPM7064SLC44-5
Device Options:
Turbo Bit = ON
Security Bit = OFF
Enable JTAG Support = ON
User Code = ffff
Device-Specific Information: d:\vhdl\i2c\i2c1.rpt
i2c1
** ERROR SUMMARY **
Info: Chip 'i2c1' in device 'EPM7064SLC44-5' has less than 10% of logic cells available for future logic changes -- if your project is likely to change, Altera recommends using a larger device
R R R
E E E
n S S S
r E E E
e R R R
s V V G G G c G V V
d e E C N N N l N E E
3 t D C D D D k D D D
-----------------------------------_
/ 6 5 4 3 2 1 44 43 42 41 40 |
#TDI | 7 39 | RESERVED
d4 | 8 38 | #TDO
d5 | 9 37 | RESERVED
GND | 10 36 | RESERVED
d6 | 11 35 | VCC
d7 | 12 EPM7064SLC44-5 34 | RESERVED
#TMS | 13 33 | RESERVED
RESERVED | 14 32 | #TCK
VCC | 15 31 | RESERVED
write | 16 30 | GND
read | 17 29 | RESERVED
|_ 18 19 20 21 22 23 24 25 26 27 28 _|
------------------------------------
s d d d G V S s R R S
t 1 0 2 N C D t E E C
o D C A a S S L
p r E E
t R R
V V
E E
D D
N.C. = No Connect. This pin has no internal connection to the device.
VCC = Dedicated power pin, which MUST be connected to VCC.
GND = Dedicated ground pin or unused dedicated input, which MUST be connected to GND.
RESERVED = Unused I/O pin, which MUST be left unconnected.
^ = Dedicated configuration pin.
+ = Reserved configuration pin, which is tri-stated during user mode.
* = Reserved configuration pin, which drives out in user mode.
PDn = Power Down pin.
@ = Special-purpose pin.
# = JTAG Boundary-Scan Testing/In-System Programming or Configuration Pin. The JTAG inputs TMS and TDI should be tied to VCC and TCK should be tied to GND when not in use.
& = JTAG pin used for I/O. When used as user I/O, JTAG pins must be kept stable before and during configuration. JTAG pin stability prevents accidental loading of JTAG instructions.
Device-Specific Information: d:\vhdl\i2c\i2c1.rpt
i2c1
** RESOURCE USAGE **
Shareable External
Logic Array Block Logic Cells I/O Pins Expanders Interconnect
A: LC1 - LC16 16/16(100%) 7/ 8( 87%) 15/16( 93%) 25/36( 69%)
B: LC17 - LC32 16/16(100%) 7/ 8( 87%) 15/16( 93%) 28/36( 77%)
C: LC33 - LC48 16/16(100%) 4/ 8( 50%) 16/16(100%) 21/36( 58%)
D: LC49 - LC64 16/16(100%) 1/ 8( 12%) 16/16(100%) 25/36( 69%)
Total dedicated input pins used: 1/4 ( 25%)
Total I/O pins used: 19/32 ( 59%)
Total logic cells used: 64/64 (100%)
Total shareable expanders used: 41/64 ( 64%)
Total Turbo logic cells used: 64/64 (100%)
Total shareable expanders not available (n/a): 21/64 ( 32%)
Average fan-in: 7.51
Total fan-in: 481
Total input pins required: 6
Total fast input logic cells required: 0
Total output pins required: 0
Total bidirectional pins required: 10
Total reserved pins required 4
Total logic cells required: 64
Total flipflops required: 54
Total product terms required: 268
Total logic cells lending parallel expanders: 0
Total shareable expanders in database: 40
Synthesized logic cells: 8/ 64 ( 12%)
Device-Specific Information: d:\vhdl\i2c\i2c1.rpt
i2c1
** INPUTS **
Shareable
Expanders Fan-In Fan-Out
Pin LC LAB Primitive Code Total Shared n/a INP FBK OUT FBK Name
43 - - INPUT G 0 0 0 0 0 0 0 clk
20 19 B BIDIR 1 1 0 0 7 1 1 d0
19 20 B BIDIR 1 1 0 0 7 1 1 d1
21 17 B BIDIR 1 1 0 0 7 1 1 d2
6 11 A BIDIR 1 1 0 0 7 1 1 d3
8 5 A BIDIR 1 1 0 0 7 1 1 d4
9 4 A BIDIR 1 1 0 0 7 1 1 d5
11 3 A BIDIR 1 1 0 0 7 1 1 d6
12 1 A BIDIR 1 1 0 0 7 1 1 d7
5 (14) (A) INPUT 0 0 0 0 0 2 26 nreset
17 (24) (B) INPUT 0 0 0 0 0 0 12 read
28 40 C BIDIR 0 0 0 1 1 0 0 SCL
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