p2s_altera.vhd

来自「这是我做的I2C的vhdl程序和仿真和下载文件」· VHDL 代码 · 共 25 行

LIBRARY altera;
USE altera.maxplus2.ALL;
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;

entity p2s_altera is
port(
  clk,
  clkih, 
  stld,
  ser: in std_logic;

 d :in std_logic_vector(0 to 7);
 q,
 nq: out std_logic

);
end p2s_altera;

architecture arc_p2s2 of p2s_altera is
begin
u1: a_74165b  port map (clk, clkih, stld, ser, d,q,nq);
end arc_p2s2;