📄 s2p2.vhd
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-- TTL164 Shift Register
-- download from: www.fpga.com.cn & www.pld.com.cn
library IEEE;
use IEEE.Std_logic_1164.all;
use ieee.std_logic_arith.all;
ENTITY s2p2 IS
PORT(
nclr,
clock : IN std_logic;
d: in std_logic;
sr: out std_logic_vector( 7 downto 0)
);
END s2p2;
ARCHITECTURE arc_p2s2 OF s2p2 IS
signal q :std_logic_vector(7 downto 0);
signal cnt: unsigned(3 downto 0);
BEGIN
PROCESS(d,nclr,clock)
BEGIN
IF nclr = '0' THEN
q <= "00000000";
cnt<="0000";
ELSE
IF clock'EVENT AND clock = '1' THEN
q(0)<=d;
cnt<="0000";
FOR i IN 1 to 7 LOOP
q(i) <= q(i-1);
cnt<=cnt +1;
END LOOP;
if(cnt=8) then
sr<=q;
cnt<="0000";
end if;
END IF;
END IF;
END PROCESS;
END arc_p2s2;
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