📄 i2c.rpt
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!state_p2s3
# !iload & state_p2s3;
-- Node name is ':48' = 'state_s2p0'
-- Equation name is 'state_s2p0', location is LC009, type is buried.
state_s2p0 = DFFE( _EQ044 $ VCC, GLOBAL( clk), VCC, VCC, VCC);
_EQ044 = ishift & state_s2p0 & !state_s2p3
# ishift & !nreset
# !ishift & !state_s2p0;
-- Node name is ':47' = 'state_s2p1'
-- Equation name is 'state_s2p1', location is LC010, type is buried.
state_s2p1 = DFFE( _EQ045 $ GND, GLOBAL( clk), VCC, VCC, VCC);
_EQ045 = ishift & nreset & state_s2p0 & !state_s2p1 & !state_s2p3
# nreset & !state_s2p0 & state_s2p1 & !state_s2p3
# !ishift & state_s2p1;
-- Node name is ':46' = 'state_s2p2'
-- Equation name is 'state_s2p2', location is LC021, type is buried.
state_s2p2 = TFFE( _EQ046, GLOBAL( clk), VCC, VCC, VCC);
_EQ046 = ishift & nreset & state_s2p0 & state_s2p1 & !state_s2p2 &
!state_s2p3
# ishift & state_s2p0 & state_s2p1 & state_s2p2
# ishift & state_s2p2 & state_s2p3
# ishift & !nreset & state_s2p2;
-- Node name is ':45' = 'state_s2p3'
-- Equation name is 'state_s2p3', location is LC022, type is buried.
state_s2p3 = DFFE( _EQ047 $ !ishift, GLOBAL( clk), VCC, VCC, VCC);
_EQ047 = ishift & nreset & state_s2p0 & state_s2p1 & state_s2p2 &
!state_s2p3
# ishift & nreset & !state_s2p0 & !state_s2p1 & !state_s2p2 &
state_s2p3
# !ishift & !state_s2p3;
-- Node name is 'state~1~1'
-- Equation name is 'state~1~1', location is LC048, type is buried.
-- synthesized logic cell
_LC048 = LCELL( _EQ048 $ GND);
_EQ048 = state~1 & !state~2 & state~4 & !state~5
# state~1 & !state~3 & !state~4 & state~5
# state~1 & !state~2 & !state~3 & !state~4
# start & !state~2 & !state~3 & !state~4
# !state~2 & !state~3 & !state~4 & state~5;
-- Node name is 'state~1'
-- Equation name is 'state~1', location is LC018, type is buried.
state~1 = DFFE( _EQ049 $ _EQ050, GLOBAL( clk), nreset, VCC, VCC);
_EQ049 = !_LC048 & !read & !state~1 & state~3 & !state~4 & !state~5 &
!write & _X020 & _X021 & _X022
# !_LC048 & !state~1 & !state~2 & !state~4 & !state~5 & stop &
_X020 & _X021 & _X022
# !_LC048 & state~1 & state~3 & state~4 & !state~5 & _X020 &
_X021 & _X022;
_X020 = EXP( state~2 & state~3 & !state~4);
_X021 = EXP(!nreset & !state~5);
_X022 = EXP(!nreset & !state~4);
_EQ050 = !_LC048 & _X020 & _X021 & _X022;
_X020 = EXP( state~2 & state~3 & !state~4);
_X021 = EXP(!nreset & !state~5);
_X022 = EXP(!nreset & !state~4);
-- Node name is 'state~2~1'
-- Equation name is 'state~2~1', location is LC027, type is buried.
-- synthesized logic cell
_LC027 = LCELL( _EQ051 $ GND);
_EQ051 = state~1 & !state~3 & !state~4 & !state~5
# !state~1 & state~3 & state~5
# state~1 & !state~2 & state~4
# !state~1 & state~2 & state~5
# !state~1 & state~2 & state~4;
-- Node name is 'state~2'
-- Equation name is 'state~2', location is LC036, type is buried.
state~2 = DFFE( _EQ052 $ _EQ053, GLOBAL( clk), nreset, VCC, VCC);
_EQ052 = idcnt0 & !idcnt1 & !idcnt2 & !_LC027 & nreset & !state~1 &
state~3 & state~4 & !stop & _X023 & _X024 & _X025
# idcnt0 & !idcnt1 & !idcnt2 & !_LC027 & nreset & !state~2 &
state~3 & state~5 & _X023 & _X024 & _X025
# !_LC027 & nreset & !read & !state~1 & state~3 & !state~4 & !stop &
!write & _X023 & _X024 & _X025;
_X023 = EXP(!state~1 & state~2 & state~3);
_X024 = EXP( state~1 & !state~2 & !state~3);
_X025 = EXP( state~4 & state~5);
_EQ053 = !_LC027 & nreset & _X023 & _X024 & _X025;
_X023 = EXP(!state~1 & state~2 & state~3);
_X024 = EXP( state~1 & !state~2 & !state~3);
_X025 = EXP( state~4 & state~5);
-- Node name is 'state~3~1'
-- Equation name is 'state~3~1', location is LC047, type is buried.
-- synthesized logic cell
_LC047 = LCELL( _EQ054 $ GND);
_EQ054 = nreset & !start & !state~1 & !state~2 & !state~3 & !state~4 &
!state~5 & !stop
# nreset & state~1 & state~2 & !state~3 & state~4 & !state~5
# !nreset & state~3 & !state~5
# !read & !state~1 & !state~2 & state~3 & !state~4 & !state~5 &
!write
# !state~1 & !state~2 & state~3 & !state~5 & stop;
-- Node name is 'state~3'
-- Equation name is 'state~3', location is LC049, type is buried.
state~3 = TFFE(!_EQ055, GLOBAL( clk), nreset, VCC, VCC);
_EQ055 = !_LC047 & _X026;
_X026 = EXP(!nreset & state~3 & !state~4);
-- Node name is 'state~4~1'
-- Equation name is 'state~4~1', location is LC046, type is buried.
-- synthesized logic cell
_LC046 = LCELL( _EQ056 $ GND);
_EQ056 = nreset & start & !state~1 & !state~2 & !state~3 & !state~4 &
!state~5
# !nreset & state~4 & !state~5
# idcnt0 & !idcnt1 & !idcnt2 & !state~1 & !state~2 & state~3 &
state~4 & !state~5
# nreset & read & !state~1 & !state~2 & !state~4 & !state~5 &
!stop & !write
# nreset & read & !state~1 & !state~2 & !state~3 & !state~4 &
!state~5 & !stop;
-- Node name is 'state~4'
-- Equation name is 'state~4', location is LC020, type is buried.
state~4 = TFFE(!_EQ057, GLOBAL( clk), nreset, VCC, VCC);
_EQ057 = !_LC046 & _X027 & _X028;
_X027 = EXP(!read & state~1 & state~2 & !state~3 & state~4 & !state~5);
_X028 = EXP(!state~1 & !state~2 & state~3 & state~4 & !state~5 & stop);
-- Node name is 'state~5~1'
-- Equation name is 'state~5~1', location is LC039, type is buried.
-- synthesized logic cell
_LC039 = LCELL( _EQ058 $ GND);
_EQ058 = nreset & !state~1 & !state~2 & state~3 & !state~4 & !state~5 &
!stop & write
# nreset & !state~1 & !state~2 & state~3 & state~4 & !state~5 &
stop
# nreset & !read & state~1 & state~2 & !state~3 & state~4 &
!state~5
# !state~1 & !state~2 & !state~3 & !state~4 & state~5
# idcnt0 & !idcnt1 & !idcnt2 & state~1 & !state~2 & state~3 &
!state~4 & state~5;
-- Node name is 'state~5'
-- Equation name is 'state~5', location is LC038, type is buried.
state~5 = TFFE(!_EQ059, GLOBAL( clk), nreset, VCC, VCC);
_EQ059 = !_LC039 & _X029 & _X030;
_X029 = EXP( nreset & !read & !start & !state~1 & !state~2 & !state~3 &
!state~4 & !stop);
_X030 = EXP(!nreset & !state~4 & state~5);
-- Node name is '~752~1'
-- Equation name is '~752~1', location is LC026, type is buried.
-- synthesized logic cell
_LC026 = LCELL( _EQ060 $ GND);
_EQ060 = state~1 & !state~2 & state~3 & !state~4
# !state~1 & state~2 & !state~3 & !state~5
# !state~1 & state~2 & !state~4 & !state~5
# !iscl & !state~2 & !state~3 & state~5
# state~1 & !state~4 & state~5;
-- Node name is '~824~1'
-- Equation name is '~824~1', location is LC023, type is buried.
-- synthesized logic cell
_LC023 = LCELL( _EQ061 $ GND);
_EQ061 = state~1 & state~2 & !state~3 & !state~5
# !state~2 & state~3 & !state~4 & !state~5
# !isda & !state~2 & state~3 & !state~4
# !isda & !state~1 & state~3 & !state~4
# !state~1 & !state~2 & !state~5;
-- Node name is '~896~1'
-- Equation name is '~896~1', location is LC044, type is buried.
-- synthesized logic cell
_LC044 = LCELL( _EQ062 $ GND);
_EQ062 = !idcnt2 & read & !state~1 & !state~2 & state~3 & !state~4 &
!state~5 & !stop
# !idcnt2 & !state~1 & !state~2 & state~3 & !state~4 & !state~5 &
!stop & write
# !idcnt2 & !start & !state~1 & !state~2 & !state~3 & !state~4 &
!state~5 & !stop
# !idcnt0 & !idcnt1 & state~1 & !state~2 & state~3 & !state~4 &
state~5
# !idcnt0 & !idcnt1 & !state~1 & !state~2 & state~3 & state~4 &
!state~5;
-- Node name is '~968~1'
-- Equation name is '~968~1', location is LC043, type is buried.
-- synthesized logic cell
_LC043 = LCELL( _EQ063 $ GND);
_EQ063 = !idcnt1 & read & !state~1 & !state~2 & state~3 & !state~4 &
!state~5 & !stop
# !idcnt1 & !state~1 & !state~2 & state~3 & !state~4 & !state~5 &
!stop & write
# !idcnt1 & !start & !state~1 & !state~2 & !state~3 & !state~4 &
!state~5 & !stop
# !idcnt1 & state~1 & state~2 & !state~3 & state~4 & !state~5
# !idcnt0 & state~1 & !state~2 & state~3 & !state~4 & state~5;
-- Node name is '~1040~1'
-- Equation name is '~1040~1', location is LC037, type is buried.
-- synthesized logic cell
_LC037 = LCELL( _EQ064 $ GND);
_EQ064 = state~1 & !state~2 & state~3 & !state~4 & state~5
# !state~1 & !state~2 & state~3 & state~4 & !state~5
# !idcnt0 & !start & !state~1 & !state~2 & !state~3 & !state~4 &
!state~5 & !stop
# !idcnt0 & !state~1 & !state~2 & state~3 & !state~5 & !stop &
write
# !idcnt0 & read & !state~1 & !state~2 & state~3 & !state~5 &
!stop;
-- Node name is '~2360~1'
-- Equation name is '~2360~1', location is LC050, type is buried.
-- synthesized logic cell
_LC050 = LCELL( _EQ065 $ GND);
_EQ065 = iload & !shifter3 & state_p2s0 & !state_p2s1 & state_p2s2 &
!state_p2s3
# iload & !shifter7 & !state_p2s1 & !state_p2s2 & !state_p2s3
# iload & !shifter6 & !state_p2s0 & !state_p2s2 & !state_p2s3
# iload & !shifter4 & !state_p2s0 & !state_p2s1 & !state_p2s3
# iload & !shifter0 & !state_p2s0 & !state_p2s1 & !state_p2s2;
-- Shareable expanders that are duplicated in multiple LABs:
-- _X001 occurs in LABs A, B
-- _X005 occurs in LABs B, D
Project Information d:\vhdl\i2c\i2c.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = on
Rules = EPLD Rules
Logic Synthesis:
Synthesis Type Used = Standard
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'MAX7000S' family
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
PARALLEL_EXPANDERS = off
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SOFT_BUFFER_INSERTION = on
SUBFACTOR_EXTRACTION = on
TURBO_BIT = on
XOR_SYNTHESIS = on
IGNORE_SOFT_BUFFERS = off
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
One-Hot State Machine Encoding = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Use Quartus Fitter = off
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:01
Database Builder 00:00:01
Logic Synthesizer 00:00:01
Partitioner 00:00:00
Fitter 00:00:01
Timing SNF Extractor 00:00:00
Assembler 00:00:03
Design Doctor 00:00:08
-------------------------- --------
Total Time 00:00:15
Memory Allocated
-----------------
Peak memory allocated during compilation = 5,989K
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