📄 i2c.rpt
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(40) 62 D DFFE + t 0 0 0 0 3 0 3 shifter3 (:36)
- 61 D DFFE + t 0 0 0 0 3 0 2 shifter2 (:37)
- 60 D DFFE + t 0 0 0 0 3 0 2 shifter1 (:38)
- 59 D DFFE + t 0 0 0 0 3 0 2 shifter0 (:39)
(38) 56 D DFFE + t 0 0 0 1 5 0 6 state_p2s3 (:40)
- 54 D DFFE + t 0 0 0 1 5 0 4 state_p2s2 (:41)
(34) 51 D DFFE + t 0 0 0 1 4 0 5 state_p2s1 (:42)
- 58 D DFFE + t 0 0 0 1 3 0 6 state_p2s0 (:43)
(39) 57 D DFFE + t 6 0 1 0 14 0 3 sr (:44)
- 22 B DFFE + t 0 0 0 1 5 8 12 state_s2p3 (:45)
(18) 21 B TFFE + t 0 0 0 1 5 8 10 state_s2p2 (:46)
- 10 A DFFE + t 0 0 0 1 4 8 11 state_s2p1 (:47)
- 9 A DFFE + t 0 0 0 1 3 8 12 state_s2p0 (:48)
- 13 A DFFE + t 3 1 1 0 7 1 2 shift7 (:49)
- 15 A DFFE + t 3 1 1 0 7 1 2 shift6 (:50)
(4) 16 A DFFE + t 3 1 1 0 7 1 2 shift5 (:51)
- 6 A DFFE + t 3 1 1 0 7 1 2 shift4 (:52)
- 7 A DFFE + t 3 1 1 0 7 1 2 shift3 (:53)
(7) 8 A DFFE + t 3 1 1 0 7 1 2 shift2 (:54)
- 12 A DFFE + t 3 1 1 0 7 1 2 shift1 (:55)
(17) 24 B DFFE + t 3 1 1 0 7 1 1 shift0 (:56)
(16) 25 B DFFE + t 3 2 1 1 7 0 3 iscl (:109)
(36) 52 D DFFE + t 2 1 1 1 7 0 1 isda (:110)
- 45 C TFFE + t 1 0 0 1 7 0 5 idcnt2 (:111)
- 42 C TFFE + t 1 0 0 1 7 0 5 idcnt1 (:112)
(29) 41 C TFFE + t 1 0 0 1 7 0 8 idcnt0 (:113)
- 26 B SOFT s t 1 0 1 0 6 0 2 ~752~1
- 23 B SOFT s t 1 0 1 0 6 0 2 ~824~1
- 44 C SOFT s t 1 0 1 4 8 0 1 ~896~1
- 43 C SOFT s t 1 0 1 4 7 0 1 ~968~1
(27) 37 C SOFT s t 1 0 1 4 6 0 1 ~1040~1
- 50 D SOFT s t 1 0 1 0 10 0 1 ~2360~1
Code:
s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
Device-Specific Information: d:\vhdl\i2c\i2c.rpt
i2c
** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'A':
Logic cells placed in LAB 'A'
+------------------------------- LC11 d2
| +----------------------------- LC5 d3
| | +--------------------------- LC4 d4
| | | +------------------------- LC14 d5
| | | | +----------------------- LC3 d6
| | | | | +--------------------- LC1 d7
| | | | | | +------------------- LC2 shifter5
| | | | | | | +----------------- LC10 state_s2p1
| | | | | | | | +--------------- LC9 state_s2p0
| | | | | | | | | +------------- LC13 shift7
| | | | | | | | | | +----------- LC15 shift6
| | | | | | | | | | | +--------- LC16 shift5
| | | | | | | | | | | | +------- LC6 shift4
| | | | | | | | | | | | | +----- LC7 shift3
| | | | | | | | | | | | | | +--- LC8 shift2
| | | | | | | | | | | | | | | +- LC12 shift1
| | | | | | | | | | | | | | | |
| | | | | | | | | | | | | | | | Other LABs fed by signals
| | | | | | | | | | | | | | | | that feed LAB 'A'
LC | | | | | | | | | | | | | | | | | A B C D | Logic cells that feed LAB 'A':
LC11 -> * - - - - - - - - - - - - - - - | * - - * | <-- d2
LC5 -> - * - - - - - - - - - - - - - - | * - - * | <-- d3
LC4 -> - - * - - - - - - - - - - - - - | * - - * | <-- d4
LC14 -> - - - * - - * - - - - - - - - - | * - - - | <-- d5
LC3 -> - - - - * - - - - - - - - - - - | * - - * | <-- d6
LC1 -> - - - - - * - - - - - - - - - - | * - - * | <-- d7
LC2 -> - - - - - - * - - - - - - - - - | * - - * | <-- shifter5
LC10 -> * * * * * * - * - * * * * * * * | * * - - | <-- state_s2p1
LC9 -> * * * * * * - * * * * * * * * * | * * - - | <-- state_s2p0
LC13 -> - - - - - * - - - * * - - - - - | * - - - | <-- shift7
LC15 -> - - - - * - - - - - * * - - - - | * - - - | <-- shift6
LC16 -> - - - * - - - - - - - * * - - - | * - - - | <-- shift5
LC6 -> - - * - - - - - - - - - * * - - | * - - - | <-- shift4
LC7 -> - * - - - - - - - - - - - * * - | * - - - | <-- shift3
LC8 -> * - - - - - - - - - - - - - * * | * - - - | <-- shift2
LC12 -> - - - - - - - - - - - - - - - * | * * - - | <-- shift1
Pin
43 -> - - - - - - - - - - - - - - - - | - - - - | <-- clk
4 -> - - - - - - - * * - - - - - - - | * * * * | <-- nreset
LC33 -> - - - - - - - - - * - - - - - - | * - - - | <-- SDA
LC35 -> * * * * * * - * * * * * * * * * | * * * - | <-- ishift
LC34 -> - - - - - - * - - - - - - - - - | * - * * | <-- iload
LC22 -> * * * * * * - * * * * * * * * * | * * - - | <-- state_s2p3
LC21 -> * * * * * * - - - * * * * * * * | * * - - | <-- state_s2p2
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).
Device-Specific Information: d:\vhdl\i2c\i2c.rpt
i2c
** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'B':
Logic cells placed in LAB 'B'
+------------------------- LC17 d0
| +----------------------- LC19 d1
| | +--------------------- LC30 SCL
| | | +------------------- LC18 state~1
| | | | +----------------- LC27 state~2~1
| | | | | +--------------- LC20 state~4
| | | | | | +------------- LC28 sclo
| | | | | | | +----------- LC22 state_s2p3
| | | | | | | | +--------- LC21 state_s2p2
| | | | | | | | | +------- LC24 shift0
| | | | | | | | | | +----- LC25 iscl
| | | | | | | | | | | +--- LC26 ~752~1
| | | | | | | | | | | | +- LC23 ~824~1
| | | | | | | | | | | | |
| | | | | | | | | | | | | Other LABs fed by signals
| | | | | | | | | | | | | that feed LAB 'B'
LC | | | | | | | | | | | | | | A B C D | Logic cells that feed LAB 'B':
LC17 -> * - - - - - - - - - - - - | - * - * | <-- d0
LC19 -> - * - - - - - - - - - - - | - * - * | <-- d1
LC18 -> - - - * * * * - - - * * * | - * * * | <-- state~1
LC20 -> - - - * * * * - - - * * * | - * * * | <-- state~4
LC28 -> - - * - - - - - - - - - - | - * - - | <-- sclo
LC22 -> * * - - - - - * * * - - - | * * - - | <-- state_s2p3
LC21 -> * * - - - - - * * * - - - | * * - - | <-- state_s2p2
LC24 -> * - - - - - - - - * - - - | - * - - | <-- shift0
LC25 -> - - - - - - * - - - * * - | - * - - | <-- iscl
LC26 -> - - - - - - * - - - * - - | - * - - | <-- ~752~1
Pin
43 -> - - - - - - - - - - - - - | - - - - | <-- clk
4 -> - - * * - * * * * - * - - | * * * * | <-- nreset
17 -> - - - * - * - - - - - - - | - * * - | <-- read
19 -> - - - * - * - - - - - - - | - * * - | <-- stop
18 -> - - - * - - - - - - - - - | - * * - | <-- write
LC48 -> - - - * - - - - - - - - - | - * - - | <-- state~1~1
LC36 -> - - - * * * * - - - * * * | - * * * | <-- state~2
LC49 -> - - - * * * * - - - * * * | - * * * | <-- state~3
LC46 -> - - - - - * - - - - - - - | - * - - | <-- state~4~1
LC38 -> - - - * * * * - - - * * * | - * * * | <-- state~5
LC35 -> * * - - - - - * * * - - - | * * * - | <-- ishift
LC10 -> * * - - - - - * * * - - - | * * - - | <-- state_s2p1
LC9 -> * * - - - - - * * * - - - | * * - - | <-- state_s2p0
LC12 -> - * - - - - - - - * - - - | * * - - | <-- shift1
LC52 -> - - - - - - - - - - - - * | - * - - | <-- isda
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).
Device-Specific Information: d:\vhdl\i2c\i2c.rpt
i2c
** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'C':
Logic cells placed in LAB 'C'
+----------------------------- LC33 SDA
| +--------------------------- LC48 state~1~1
| | +------------------------- LC36 state~2
| | | +----------------------- LC47 state~3~1
| | | | +--------------------- LC46 state~4~1
| | | | | +------------------- LC39 state~5~1
| | | | | | +----------------- LC38 state~5
| | | | | | | +--------------- LC35 ishift
| | | | | | | | +------------- LC34 iload
| | | | | | | | | +----------- LC45 idcnt2
| | | | | | | | | | +--------- LC42 idcnt1
| | | | | | | | | | | +------- LC41 idcnt0
| | | | | | | | | | | | +----- LC44 ~896~1
| | | | | | | | | | | | | +--- LC43 ~968~1
| | | | | | | | | | | | | | +- LC37 ~1040~1
| | | | | | | | | | | | | | |
| | | | | | | | | | | | | | | Other LABs fed by signals
| | | | | | | | | | | | | | | that feed LAB 'C'
LC | | | | | | | | | | | | | | | | A B C D | Logic cells that feed LAB 'C':
LC36 -> - * * * * * * * * * * * * * * | - * * * | <-- state~2
LC39 -> - - - - - - * - - - - - - - - | - - * - | <-- state~5~1
LC38 -> - * * * * * * * * * * * * * * | - * * * | <-- state~5
LC35 -> - - - - - - - * - - - - - - - | * * * - | <-- ishift
LC34 -> - - - - - - - - * - - - - - - | * - * * | <-- iload
LC45 -> - - * - * * - - - * - - * - - | - - * - | <-- idcnt2
LC42 -> - - * - * * - - - - * - * * - | - - * - | <-- idcnt1
LC41 -> - - * - * * - - - - * * * * * | - - * - | <-- idcnt0
LC44 -> - - - - - - - - - * - - - - - | - - * - | <-- ~896~1
LC43 -> - - - - - - - - - - * - - - - | - - * - | <-- ~968~1
LC37 -> - - - - - - - - - - - * - - - | - - * - | <-- ~1040~1
Pin
43 -> - - - - - - - - - - - - - - - | - - - - | <-- clk
4 -> * - * * * * * * * * * * - - - | * * * * | <-- nreset
17 -> - - * * * * * * * - - - * * * | - * * - | <-- read
16 -> - * - * * - * * * - - - * * * | - - * - | <-- start
19 -> - - * * * * * * * - - - * * * | - * * - | <-- stop
18 -> - - * * * * - * * - - - * * * | - * * - | <-- write
LC18 -> - * * * * * * * * * * * * * * | - * * * | <-- state~1
LC27 -> - - * - - - - - - - - - - - - | - - * - | <-- state~2~1
LC49 -> - * * * * * * * * * * * * * * | - * * * | <-- state~3
LC20 -> - * * * * * * * * * * * * * * | - * * * | <-- state~4
LC63 -> * - - - - - - - - - - - - - - | - - * - | <-- sdao
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).
Device-Specific Information: d:\vhdl\i2c\i2c.rpt
i2c
** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'D':
Logic cells placed in LAB 'D'
+------------------------------- LC49 state~3
| +----------------------------- LC63 sdao
| | +--------------------------- LC55 shifter7
| | | +------------------------- LC53 shifter6
| | | | +----------------------- LC64 shifter4
| | | | | +--------------------- LC62 shifter3
| | | | | | +------------------- LC61 shifter2
| | | | | | | +----------------- LC60 shifter1
| | | | | | | | +--------------- LC59 shifter0
| | | | | | | | | +------------- LC56 state_p2s3
| | | | | | | | | | +----------- LC54 state_p2s2
| | | | | | | | | | | +--------- LC51 state_p2s1
| | | | | | | | | | | | +------- LC58 state_p2s0
| | | | | | | | | | | | | +----- LC57 sr
| | | | | | | | | | | | | | +--- LC52 isda
| | | | | | | | | | | | | | | +- LC50 ~2360~1
| | | | | | | | | | | | | | | |
| | | | | | | | | | | | | | | | Other LABs fed by signals
| | | | | | | | | | | | | | | | that feed LAB 'D'
LC | | | | | | | | | | | | | | | | | A B C D | Logic cells that feed LAB 'D':
LC49 -> * * - - - - - - - - - - - - * - | - * * * | <-- state~3
LC55 -> - - * - - - - - - - - - - * - * | - - - * | <-- shifter7
LC53 -> - - - * - - - - - - - - - * - * | - - - * | <-- shifter6
LC64 -> - - - - * - - - - - - - - * - * | - - - * | <-- shifter4
LC62 -> - - - - - * - - - - - - - * - * | - - - * | <-- shifter3
LC61 -> - - - - - - * - - - - - - * - - | - - - * | <-- shifter2
LC60 -> - - - - - - - * - - - - - * - - | - - - * | <-- shifter1
LC59 -> - - - - - - - - * - - - - - - * | - - - * | <-- shifter0
LC56 -> - - - - - - - - - * * * * * - * | - - - * | <-- state_p2s3
LC54 -> - - - - - - - - - * * - - * - * | - - - * | <-- state_p2s2
LC51 -> - - - - - - - - - * * * - * - * | - - - * | <-- state_p2s1
LC58 -> - - - - - - - - - * * * * * - * | - - - * | <-- state_p2s0
LC57 -> - * - - - - - - - - - - - * * - | - - - * | <-- sr
LC50 -> - - - - - - - - - - - - - * - - | - - - * | <-- ~2360~1
Pin
43 -> - - - - - - - - - - - - - - - - | - - - - | <-- clk
4 -> * * - - - - - - - * * * * - * - | * * * * | <-- nreset
LC17 -> - - - - - - - - * - - - - - - - | - * - * | <-- d0
LC19 -> - - - - - - - * - - - - - - - - | - * - * | <-- d1
LC11 -> - - - - - - * - - - - - - - - - | * - - * | <-- d2
LC5 -> - - - - - * - - - - - - - - - - | * - - * | <-- d3
LC4 -> - - - - * - - - - - - - - - - - | * - - * | <-- d4
LC3 -> - - - * - - - - - - - - - - - - | * - - * | <-- d6
LC1 -> - - * - - - - - - - - - - - - - | * - - * | <-- d7
LC18 -> - * - - - - - - - - - - - - * - | - * * * | <-- state~1
LC36 -> - * - - - - - - - - - - - - * - | - * * * | <-- state~2
LC47 -> * - - - - - - - - - - - - - - - | - - - * | <-- state~3~1
LC20 -> * * - - - - - - - - - - - - * - | - * * * | <-- state~4
LC38 -> - * - - - - - - - - - - - - * - | - * * * | <-- state~5
LC34 -> - - * * * * * * * * * * * * - * | * - * * | <-- iload
LC2 -> - - - - - - - - - - - - - * - - | * - - * | <-- shifter5
LC23 -> - * - - - - - - - - - - - - * - | - - - * | <-- ~824~1
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).
Device-Specific Information: d:\vhdl\i2c\i2c.rpt
i2c
** EQUATIONS **
clk : INPUT;
nreset : INPUT;
read : INPUT;
start : INPUT;
stop : INPUT;
write : INPUT;
-- Node name is 'd0' = ':17'
-- Equation name is 'd0', type is bidir
d0 = TRI(_LC017, VCC);
_LC017 = DFFE( _EQ001 $ d0, GLOBAL( clk), VCC, VCC, VCC);
_EQ001 = !d0 & ishift & shift0 & state_s2p3 & _X001
# d0 & ishift & !shift0 & state_s2p3 & _X001;
_X001 = EXP(!state_s2p0 & !state_s2p1 & !state_s2p2);
-- Node name is 'd1' = ':15'
-- Equation name is 'd1', type is bidir
d1 = TRI(_LC019, VCC);
_LC019 = DFFE( _EQ002 $ d1, GLOBAL( clk), VCC, VCC, VCC);
_EQ002 = !d1 & ishift & shift1 & state_s2p3 & _X001
# d1 & ishift & !shift1 & state_s2p3 & _X001;
_X001 = EXP(!state_s2p0 & !state_s2p1 & !state_s2p2);
-- Node name is 'd2' = ':13'
-- Equation name is 'd2', type is bidir
d2 = TRI(_LC011, VCC);
_LC011 = DFFE( _EQ003 $ d2, GLOBAL( clk), VCC, VCC, VCC);
_EQ003 = !d2 & ishift & shift2 & state_s2p3 & _X001
# d2 & ishift & !shift2 & state_s2p3 & _X001;
_X001 = EXP(!state_s2p0 & !state_s2p1 & !state_s2p2);
-- Node name is 'd3' = ':11'
-- Equation name is 'd3', type is bidir
d3 = TRI(_LC005, VCC);
_LC005 = DFFE( _EQ004 $ d3, GLOBAL( clk), VCC, VCC, VCC);
_EQ004 = !d3 & ishift & shift3 & state_s2p3 & _X001
# d3 & ishift & !shift3 & state_s2p3 & _X001;
_X001 = EXP(!state_s2p0 & !state_s2p1 & !state_s2p2);
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