📄 i2c_read.rpt
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_X016 = EXP(!state~2 & state~3 & state~5);
_X017 = EXP(!nreset & !state~3);
_X018 = EXP(!nreset & !state~5);
-- Node name is 'state~3'
-- Equation name is 'state~3', location is LC034, type is buried.
state~3 = TFFE( _EQ021, GLOBAL( clk), nreset, VCC, VCC);
_EQ021 = nreset & !read & !start & !state~1 & !state~2 & !state~3 &
!state~4 & !state~5 & !stop
# nreset & !read & !state~1 & state~2 & !state~3 & state~4 &
!state~5 & !stop
# !state~1 & !state~2 & state~3 & !state~4 & !state~5 & !write
# state~3 & !state~5 & _X019;
_X019 = EXP( nreset & !stop);
-- Node name is 'state~4~1'
-- Equation name is 'state~4~1', location is LC046, type is buried.
-- synthesized logic cell
_LC046 = LCELL( _EQ022 $ GND);
_EQ022 = nreset & start & !state~1 & !state~2 & !state~3 & !state~4 &
!state~5
# nreset & !state~1 & !state~2 & state~3 & !state~4 & !state~5 &
!stop & write
# !nreset & state~4 & !state~5
# !state~1 & state~2 & !state~3 & state~4 & state~5
# idcnt0 & !idcnt1 & !idcnt2 & nreset & state~1 & state~2 &
!state~3 & !state~4 & state~5 & !stop;
-- Node name is 'state~4'
-- Equation name is 'state~4', location is LC023, type is buried.
state~4 = TFFE(!_EQ023, GLOBAL( clk), nreset, VCC, VCC);
_EQ023 = !_LC046 & _X020 & _X021 & _X022 & _X023 & _X024 & _X025;
_X020 = EXP( idcnt0 & !idcnt1 & !idcnt2 & state~1 & state~2 & state~3 &
state~4 & !state~5);
_X021 = EXP( nreset & !read & !state~1 & !state~2 & !state~3 & !state~4 &
!state~5 & !stop);
_X022 = EXP( read & !state~1 & state~2 & !state~3 & state~4);
_X023 = EXP( state~4 & !state~5 & stop);
_X024 = EXP(!state~3 & state~4 & stop);
_X025 = EXP(!nreset & !state~3 & state~4);
-- Node name is 'state~5'
-- Equation name is 'state~5', location is LC038, type is buried.
state~5 = TFFE( _EQ024, GLOBAL( clk), nreset, VCC, VCC);
_EQ024 = nreset & read & !start & !state~1 & !state~2 & !state~3 &
!state~4 & !state~5 & !stop
# nreset & read & !state~1 & state~2 & !state~3 & state~4 &
!state~5 & !stop
# !read & !state~1 & state~2 & !state~3 & state~4 & state~5
# !state~3 & state~5 & _X019;
_X019 = EXP( nreset & !stop);
-- Node name is '|s2p2:shift|:31' = '|s2p2:shift|cnt0'
-- Equation name is '_LC059', type is buried
_LC059 = TFFE(!_EQ025, GLOBAL( clk), nreset, VCC, VCC);
_EQ025 = !_LC042 & !_LC044 & _LC050 & !_LC059;
-- Node name is '|s2p2:shift|:30' = '|s2p2:shift|cnt1'
-- Equation name is '_LC044', type is buried
_LC044 = TFFE( _LC059, GLOBAL( clk), nreset, VCC, VCC);
-- Node name is '|s2p2:shift|:29' = '|s2p2:shift|cnt2'
-- Equation name is '_LC042', type is buried
_LC042 = TFFE( _EQ026, GLOBAL( clk), nreset, VCC, VCC);
_EQ026 = _LC044 & _LC059;
-- Node name is '|s2p2:shift|:28' = '|s2p2:shift|cnt3'
-- Equation name is '_LC050', type is buried
_LC050 = DFFE( _EQ027 $ _LC060, GLOBAL( clk), nreset, VCC, VCC);
_EQ027 = !_LC042 & !_LC044 & _LC050 & !_LC059 & _LC060;
-- Node name is '|s2p2:shift|LPM_ADD_SUB:743|addcore:adder|addcore:adder0|result_node3' from file "addcore.tdf" line 164, column 16
-- Equation name is '_LC060', type is buried
_LC060 = LCELL( _LC050 $ _EQ028);
_EQ028 = _LC042 & _LC044 & _LC059;
-- Node name is '|s2p2:shift|:27' = '|s2p2:shift|q0'
-- Equation name is '_LC048', type is buried
_LC048 = DFFE( sda $ GND, GLOBAL( clk), nreset, VCC, VCC);
-- Node name is '|s2p2:shift|:26' = '|s2p2:shift|q1'
-- Equation name is '_LC058', type is buried
_LC058 = DFFE( _LC048 $ GND, GLOBAL( clk), nreset, VCC, VCC);
-- Node name is '|s2p2:shift|:25' = '|s2p2:shift|q2'
-- Equation name is '_LC063', type is buried
_LC063 = DFFE( _LC058 $ GND, GLOBAL( clk), nreset, VCC, VCC);
-- Node name is '|s2p2:shift|:24' = '|s2p2:shift|q3'
-- Equation name is '_LC047', type is buried
_LC047 = DFFE( _LC063 $ GND, GLOBAL( clk), nreset, VCC, VCC);
-- Node name is '|s2p2:shift|:23' = '|s2p2:shift|q4'
-- Equation name is '_LC056', type is buried
_LC056 = DFFE( _LC047 $ GND, GLOBAL( clk), nreset, VCC, VCC);
-- Node name is '|s2p2:shift|:22' = '|s2p2:shift|q5'
-- Equation name is '_LC055', type is buried
_LC055 = DFFE( _LC056 $ GND, GLOBAL( clk), nreset, VCC, VCC);
-- Node name is '|s2p2:shift|:21' = '|s2p2:shift|q6'
-- Equation name is '_LC054', type is buried
_LC054 = DFFE( _LC055 $ GND, GLOBAL( clk), nreset, VCC, VCC);
-- Node name is '|s2p2:shift|:20' = '|s2p2:shift|q7'
-- Equation name is '_LC061', type is buried
_LC061 = DFFE( _LC054 $ GND, GLOBAL( clk), nreset, VCC, VCC);
-- Node name is '~1261~1'
-- Equation name is '~1261~1', location is LC041, type is buried.
-- synthesized logic cell
_LC041 = LCELL( _EQ029 $ GND);
_EQ029 = !idcnt2 & !state~1 & !state~2 & state~3 & !state~4 & !state~5 &
!stop & write
# !idcnt2 & !start & !state~1 & !state~2 & !state~3 & !state~4 &
!state~5 & !stop
# !idcnt0 & !idcnt1 & state~1 & state~2 & state~3 & state~4 &
!state~5
# !idcnt2 & read & !state~1 & state~2 & !state~3 & state~4 &
!stop
# !idcnt0 & !idcnt1 & state~1 & state~2 & !state~3 & !state~4 &
state~5;
-- Node name is '~1333~1'
-- Equation name is '~1333~1', location is LC043, type is buried.
-- synthesized logic cell
_LC043 = LCELL( _EQ030 $ GND);
_EQ030 = !idcnt1 & !state~1 & !state~2 & state~3 & !state~4 & !state~5 &
!stop & write
# !idcnt1 & !start & !state~1 & !state~2 & !state~3 & !state~4 &
!state~5 & !stop
# !idcnt1 & read & !state~1 & state~2 & !state~3 & state~4 &
!stop
# !idcnt1 & !state~1 & state~2 & !state~3 & state~4 & !state~5 &
!stop
# !idcnt0 & state~1 & state~2 & state~3 & state~4 & !state~5;
-- Node name is '~1405~1'
-- Equation name is '~1405~1', location is LC045, type is buried.
-- synthesized logic cell
_LC045 = LCELL( _EQ031 $ GND);
_EQ031 = state~1 & state~2 & state~3 & state~4 & !state~5
# state~1 & state~2 & !state~3 & !state~4 & state~5
# !idcnt0 & !state~1 & !state~2 & state~3 & !state~4 & !state~5 &
!stop & write
# !idcnt0 & !start & !state~1 & !state~2 & !state~3 & !state~4 &
!state~5 & !stop
# !idcnt0 & read & !state~1 & state~2 & !state~3 & state~4 &
!stop;
-- Shareable expanders that are duplicated in multiple LABs:
-- (none)
Project Information d:\vhdl\i2c\i2c_read.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = on
Rules = EPLD Rules
Logic Synthesis:
Synthesis Type Used = Standard
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'MAX7000S' family
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
PARALLEL_EXPANDERS = off
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SOFT_BUFFER_INSERTION = on
SUBFACTOR_EXTRACTION = on
TURBO_BIT = on
XOR_SYNTHESIS = on
IGNORE_SOFT_BUFFERS = off
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
One-Hot State Machine Encoding = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Use Quartus Fitter = off
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:03
Database Builder 00:00:01
Logic Synthesizer 00:00:02
Partitioner 00:00:00
Fitter 00:00:01
Timing SNF Extractor 00:00:00
Assembler 00:00:04
Design Doctor 00:00:07
-------------------------- --------
Total Time 00:00:18
Memory Allocated
-----------------
Peak memory allocated during compilation = 11,093K
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