📄 i2c_read.rpt
字号:
* = Reserved configuration pin, which drives out in user mode.
PDn = Power Down pin.
@ = Special-purpose pin.
# = JTAG Boundary-Scan Testing/In-System Programming or Configuration Pin. The JTAG inputs TMS and TDI should be tied to VCC and TCK should be tied to GND when not in use.
& = JTAG pin used for I/O. When used as user I/O, JTAG pins must be kept stable before and during configuration. JTAG pin stability prevents accidental loading of JTAG instructions.
Device-Specific Information: d:\vhdl\i2c\i2c_read.rpt
i2c_read
** RESOURCE USAGE **
Shareable External
Logic Array Block Logic Cells I/O Pins Expanders Interconnect
A: LC1 - LC16 2/16( 12%) 8/ 8(100%) 7/16( 43%) 7/36( 19%)
B: LC17 - LC32 5/16( 31%) 1/ 8( 12%) 13/16( 81%) 15/36( 41%)
C: LC33 - LC48 14/16( 87%) 2/ 8( 25%) 16/16(100%) 22/36( 61%)
D: LC49 - LC64 16/16(100%) 8/ 8(100%) 0/16( 0%) 20/36( 55%)
Total dedicated input pins used: 1/4 ( 25%)
Total I/O pins used: 19/32 ( 59%)
Total logic cells used: 37/64 ( 57%)
Total shareable expanders used: 25/64 ( 39%)
Total Turbo logic cells used: 37/64 ( 57%)
Total shareable expanders not available (n/a): 11/64 ( 17%)
Average fan-in: 7.56
Total fan-in: 280
Total input pins required: 7
Total fast input logic cells required: 0
Total output pins required: 9
Total bidirectional pins required: 0
Total reserved pins required 4
Total logic cells required: 37
Total flipflops required: 30
Total product terms required: 141
Total logic cells lending parallel expanders: 0
Total shareable expanders in database: 25
Synthesized logic cells: 6/ 64 ( 9%)
Device-Specific Information: d:\vhdl\i2c\i2c_read.rpt
i2c_read
** INPUTS **
Shareable
Expanders Fan-In Fan-Out
Pin LC LAB Primitive Code Total Shared n/a INP FBK OUT FBK Name
43 - - INPUT G 0 0 0 0 0 0 0 clk
12 (1) (A) INPUT 0 0 0 0 0 9 23 nreset
11 (3) (A) INPUT 0 0 0 0 0 0 10 read
6 (11) (A) INPUT 0 0 0 0 0 0 1 sda
8 (5) (A) INPUT 0 0 0 0 0 0 7 start
9 (4) (A) INPUT 0 0 0 0 0 0 14 stop
5 (14) (A) INPUT 0 0 0 0 0 0 6 write
Code:
s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
G = Global Source. Fan-out destinations counted here do not include destinations
that are driven using global routing resources. Refer to the Auto Global Signals,
Clock Signals, Clear Signals, Synchronous Load Signals, and Synchronous Clear Signals
Sections of this Report File for information on which signals' fan-outs are used as
Clock, Clear, Preset, Output Enable, and synchronous Load signals.
Device-Specific Information: d:\vhdl\i2c\i2c_read.rpt
i2c_read
** OUTPUTS **
Shareable
Expanders Fan-In Fan-Out
Pin LC LAB Primitive Code Total Shared n/a INP FBK OUT FBK Name
40 62 D FF + t 0 0 0 1 6 1 0 d0
41 64 D FF + t 0 0 0 1 6 1 0 d1
24 33 C FF + t 0 0 0 1 6 1 0 d2
39 57 D FF + t 0 0 0 1 6 1 0 d3
33 49 D FF + t 0 0 0 1 6 1 0 d4
36 52 D FF + t 0 0 0 1 6 1 0 d5
37 53 D FF + t 0 0 0 1 6 1 0 d6
34 51 D FF + t 0 0 0 1 6 1 0 d7
4 16 A FF + t 6 5 1 1 6 0 0 scl
Code:
s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
Device-Specific Information: d:\vhdl\i2c\i2c_read.rpt
i2c_read
** BURIED LOGIC **
Shareable
Expanders Fan-In Fan-Out
Pin LC LAB Primitive Code Total Shared n/a INP FBK OUT FBK Name
(27) 37 C SOFT s t 1 0 1 2 8 0 1 state~1~1
(26) 36 C DFFE + t 3 0 0 3 6 1 15 state~1
(19) 20 B SOFT s t 1 0 1 1 5 0 1 state~2~1
(25) 35 C DFFE + t 5 0 1 4 6 1 15 state~2
- 34 C TFFE + t 2 1 1 5 5 1 15 state~3
(31) 46 C SOFT s t 1 0 1 4 8 0 1 state~4~1
- 23 B TFFE + t 6 0 0 3 9 1 15 state~4
- 38 C TFFE + t 2 1 1 4 5 1 15 state~5
- 60 D SOFT t 0 0 0 0 4 0 1 |s2p2:shift|LPM_ADD_SUB:743|addcore:adder|addcore:adder0|result_node3
- 61 D DFFE + t 0 0 0 1 1 1 0 |s2p2:shift|q7 (|s2p2:shift|:20)
- 54 D DFFE + t 0 0 0 1 1 1 1 |s2p2:shift|q6 (|s2p2:shift|:21)
- 55 D DFFE + t 0 0 0 1 1 1 1 |s2p2:shift|q5 (|s2p2:shift|:22)
(38) 56 D DFFE + t 0 0 0 1 1 1 1 |s2p2:shift|q4 (|s2p2:shift|:23)
- 47 C DFFE + t 0 0 0 1 1 1 1 |s2p2:shift|q3 (|s2p2:shift|:24)
- 63 D DFFE + t 0 0 0 1 1 1 1 |s2p2:shift|q2 (|s2p2:shift|:25)
- 58 D DFFE + t 0 0 0 1 1 1 1 |s2p2:shift|q1 (|s2p2:shift|:26)
(32) 48 C DFFE + t 0 0 0 2 0 1 1 |s2p2:shift|q0 (|s2p2:shift|:27)
- 50 D DFFE + t 0 0 0 1 5 8 3 |s2p2:shift|cnt3 (|s2p2:shift|:28)
- 42 C TFFE + t 0 0 0 1 2 8 3 |s2p2:shift|cnt2 (|s2p2:shift|:29)
- 44 C TFFE + t 0 0 0 1 1 8 4 |s2p2:shift|cnt1 (|s2p2:shift|:30)
- 59 D TFFE + t 0 0 0 1 4 8 5 |s2p2:shift|cnt0 (|s2p2:shift|:31)
- 2 A DFFE + t 6 5 1 1 6 1 1 iscl (:77)
- 27 B TFFE + t 2 0 0 3 7 0 5 idcnt2 (:79)
- 18 B TFFE + t 2 0 0 3 8 0 6 idcnt1 (:80)
(20) 19 B TFFE + t 2 0 0 3 7 0 8 idcnt0 (:81)
(29) 41 C SOFT s t 1 0 1 4 8 0 1 ~1261~1
- 43 C SOFT s t 1 0 1 4 7 0 1 ~1333~1
- 45 C SOFT s t 1 0 1 4 6 0 1 ~1405~1
Code:
s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
Device-Specific Information: d:\vhdl\i2c\i2c_read.rpt
i2c_read
** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'A':
Logic cells placed in LAB 'A'
+--- LC16 scl
| +- LC2 iscl
| |
| | Other LABs fed by signals
| | that feed LAB 'A'
LC | | | A B C D | Logic cells that feed LAB 'A':
LC2 -> * * | * - - - | <-- iscl
Pin
43 -> - - | - - - - | <-- clk
12 -> * * | * * * * | <-- nreset
LC36 -> * * | * * * - | <-- state~1
LC35 -> * * | * * * - | <-- state~2
LC34 -> * * | * * * - | <-- state~3
LC23 -> * * | * * * - | <-- state~4
LC38 -> * * | * * * - | <-- state~5
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).
Device-Specific Information: d:\vhdl\i2c\i2c_read.rpt
i2c_read
** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'B':
Logic cells placed in LAB 'B'
+--------- LC20 state~2~1
| +------- LC23 state~4
| | +----- LC27 idcnt2
| | | +--- LC18 idcnt1
| | | | +- LC19 idcnt0
| | | | |
| | | | | Other LABs fed by signals
| | | | | that feed LAB 'B'
LC | | | | | | A B C D | Logic cells that feed LAB 'B':
LC23 -> * * * * * | * * * - | <-- state~4
LC27 -> - * * - - | - * * - | <-- idcnt2
LC18 -> - * - * - | - * * - | <-- idcnt1
LC19 -> - * - * * | - * * - | <-- idcnt0
Pin
43 -> - - - - - | - - - - | <-- clk
12 -> - * * * * | * * * * | <-- nreset
11 -> - * * * * | - * * - | <-- read
9 -> * * * * * | - * * - | <-- stop
LC36 -> * * * * * | * * * - | <-- state~1
LC35 -> * * * * * | * * * - | <-- state~2
LC34 -> * * * * * | * * * - | <-- state~3
LC46 -> - * - - - | - * - - | <-- state~4~1
LC38 -> * * * * * | * * * - | <-- state~5
LC41 -> - - * - - | - * - - | <-- ~1261~1
LC43 -> - - - * - | - * - - | <-- ~1333~1
LC45 -> - - - - * | - * - - | <-- ~1405~1
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).
Device-Specific Information: d:\vhdl\i2c\i2c_read.rpt
i2c_read
** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'C':
Logic cells placed in LAB 'C'
+--------------------------- LC33 d2
| +------------------------- LC37 state~1~1
| | +----------------------- LC36 state~1
| | | +--------------------- LC35 state~2
| | | | +------------------- LC34 state~3
| | | | | +----------------- LC46 state~4~1
| | | | | | +--------------- LC38 state~5
| | | | | | | +------------- LC47 |s2p2:shift|q3
| | | | | | | | +----------- LC48 |s2p2:shift|q0
| | | | | | | | | +--------- LC42 |s2p2:shift|cnt2
| | | | | | | | | | +------- LC44 |s2p2:shift|cnt1
| | | | | | | | | | | +----- LC41 ~1261~1
| | | | | | | | | | | | +--- LC43 ~1333~1
| | | | | | | | | | | | | +- LC45 ~1405~1
| | | | | | | | | | | | | |
| | | | | | | | | | | | | | Other LABs fed by signals
| | | | | | | | | | | | | | that feed LAB 'C'
LC | | | | | | | | | | | | | | | A B C D | Logic cells that feed LAB 'C':
LC33 -> * - - - - - - - - - - - - - | - - * - | <-- d2
LC37 -> - - * - - - - - - - - - - - | - - * - | <-- state~1~1
LC36 -> - * * * * * * - - - - * * * | * * * - | <-- state~1
LC35 -> - * * * * * * - - - - * * * | * * * - | <-- state~2
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