select7.vhd

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            library ieee;
            use ieee.std_logic_1164.all;
            use ieee.std_logic_unsigned.all;

            ENTITY select7 IS
                PORT
                (    m: IN    std_logic_vector(6 downto 0);
                    p,s    : buffer std_logic);
                
            END select7;

            ARCHITECTURE behave OF select7 IS
            BEGIN
            
                PROCESS (m)
                     variable a:std_logic_vector(2 downto 0);
                BEGIN
                         a:="000";
                    for i in 0 to 6 loop
                            if(m(i)='1') then
                               a:=a+1;
                            else
                               a:=a+0;
                            end if;
                          end loop;    
                        p<=a(2);
                        s<=not(p);
                END PROCESS;
             END behave;