cnt10.vhd

来自「测频器」· VHDL 代码 · 共 33 行

--Author    	: 屈峥 2002081212
--File Name 	: cnt10.vhd
--Objective 	: 10进制计数器
--
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY CNT10 IS
   PORT (CLK,RST,EN : IN STD_LOGIC;
         CQ : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
         COUT : OUT STD_LOGIC);
END CNT10;
ARCHITECTURE BEHAV OF CNT10 IS
BEGIN
   PROCESS(CLK,RST,EN)
      VARIABLE CQI : STD_LOGIC_VECTOR(3 DOWNTO 0);
   BEGIN
      IF RST = '1' THEN CQI := (OTHERS => '0');
      ELSIF CLK'EVENT AND CLK = '1' THEN
         IF EN = '1' THEN
            IF CQI < "1001" THEN CQI := CQI + 1;
            ELSE CQI := (OTHERS => '0');
            END IF;
         END IF;
      END IF;
      IF CQI = "1001" THEN COUT <= '1';
         ELSE COUT <= '0';
      END IF;
      CQ <= CQI;
   END PROCESS;
END BEHAV;