reg4b.vhd

来自「测频器」· VHDL 代码 · 共 21 行

--Author    	: 屈峥 2002081212
--File Name 	: reg4b.vhd
--Objective 	: 4位锁存器
--
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY REG4B IS
   PORT ( LOAD : IN STD_LOGIC;
          DIN : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
          DOUT : OUT STD_LOGIC_VECTOR(3 DOWNTO 0));
END REG4B;
ARCHITECTURE BEHAV OF REG4B IS
BEGIN 
   PROCESS (LOAD,DIN)
      BEGIN
         IF LOAD'EVENT AND LOAD = '1' THEN DOUT <= DIN;
         END IF;
   END PROCESS;
END BEHAV;