fpqandtest.rpt

测频器

Column FastTrack Interconnect:

         FastTrack                                 
Column  Interconnect    Input Pins     Output Pins     Bidir Pins
01:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
02:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
03:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
04:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
05:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
06:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
07:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
08:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
09:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
10:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
11:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
12:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
13:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
14:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
15:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
16:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
17:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
18:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
19:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
20:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
21:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
22:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
23:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
24:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
EA:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)


Device-Specific Information:    h:\eda\max+plus ii\besteve\test\fpqandtest.rpt
fpqandtest

** CLOCK SIGNALS **

Type     Fan-out       Name
INPUT       11         F1KHZ
LCELL        4         |FENPINQI:10|:494


Device-Specific Information:    h:\eda\max+plus ii\besteve\test\fpqandtest.rpt
fpqandtest

** EQUATIONS **

F1KHZ    : INPUT;

-- Node name is 'CLK' 
-- Equation name is 'CLK', type is output 
CLK      =  _LC4_C20;

-- Node name is 'CLK~1' 
-- Equation name is 'CLK~1', location is LC4_C20, type is buried.
-- synthesized logic cell 
_LC4_C20 = LCELL( F1KHZ);

-- Node name is 'CNT_EN' 
-- Equation name is 'CNT_EN', type is output 
CNT_EN   =  _LC8_A24;

-- Node name is 'LORD' 
-- Equation name is 'LORD', type is output 
LORD     = !_LC3_A24;

-- Node name is 'RST' 
-- Equation name is 'RST', type is output 
RST      =  _LC1_A24;

-- Node name is '|FENPINQI:10|:13' = '|FENPINQI:10|COUT0' 
-- Equation name is '_LC4_A13', type is buried 
_LC4_A13 = DFFE( _EQ001, GLOBAL( F1KHZ),  VCC,  VCC,  VCC);
  _EQ001 = !_LC4_A13 &  _LC4_A23;

-- Node name is '|FENPINQI:10|:12' = '|FENPINQI:10|COUT1' 
-- Equation name is '_LC3_A13', type is buried 
_LC3_A13 = DFFE( _EQ002, GLOBAL( F1KHZ),  VCC,  VCC,  VCC);
  _EQ002 = !_LC3_A13 &  _LC4_A13 &  _LC4_A23
         #  _LC3_A13 & !_LC4_A13 &  _LC4_A23;

-- Node name is '|FENPINQI:10|:11' = '|FENPINQI:10|COUT2' 
-- Equation name is '_LC5_A13', type is buried 
_LC5_A13 = DFFE( _EQ003, GLOBAL( F1KHZ),  VCC,  VCC,  VCC);
  _EQ003 = !_LC4_A13 &  _LC4_A23 &  _LC5_A13
         # !_LC3_A13 &  _LC4_A23 &  _LC5_A13
         #  _LC3_A13 &  _LC4_A13 &  _LC4_A23 & !_LC5_A13;

-- Node name is '|FENPINQI:10|:10' = '|FENPINQI:10|COUT3' 
-- Equation name is '_LC1_A23', type is buried 
_LC1_A23 = DFFE( _EQ004, GLOBAL( F1KHZ),  VCC,  VCC,  VCC);
  _EQ004 =  _LC1_A23 & !_LC2_A13 &  _LC4_A23
         # !_LC1_A23 &  _LC2_A13 &  _LC4_A23;

-- Node name is '|FENPINQI:10|:9' = '|FENPINQI:10|COUT4' 
-- Equation name is '_LC2_A23', type is buried 
_LC2_A23 = DFFE( _EQ005, GLOBAL( F1KHZ),  VCC,  VCC,  VCC);
  _EQ005 = !_LC1_A23 &  _LC2_A23 &  _LC4_A23
         # !_LC2_A13 &  _LC2_A23 &  _LC4_A23
         #  _LC1_A23 &  _LC2_A13 & !_LC2_A23 &  _LC4_A23;

-- Node name is '|FENPINQI:10|:8' = '|FENPINQI:10|COUT5' 
-- Equation name is '_LC5_A17', type is buried 
_LC5_A17 = DFFE( _EQ006, GLOBAL( F1KHZ),  VCC,  VCC,  VCC);
  _EQ006 = !_LC2_A23 &  _LC4_A23 &  _LC5_A17
         #  _LC4_A23 &  _LC5_A17 & !_LC5_A23
         #  _LC2_A23 &  _LC4_A23 & !_LC5_A17 &  _LC5_A23;

-- Node name is '|FENPINQI:10|:7' = '|FENPINQI:10|COUT6' 
-- Equation name is '_LC7_A17', type is buried 
_LC7_A17 = DFFE( _EQ007, GLOBAL( F1KHZ),  VCC,  VCC,  VCC);
  _EQ007 = !_LC1_A17 &  _LC4_A23 &  _LC7_A17
         #  _LC1_A17 &  _LC4_A23 & !_LC7_A17;

-- Node name is '|FENPINQI:10|:6' = '|FENPINQI:10|COUT7' 
-- Equation name is '_LC6_A17', type is buried 
_LC6_A17 = DFFE( _EQ008, GLOBAL( F1KHZ),  VCC,  VCC,  VCC);
  _EQ008 =  _LC4_A23 &  _LC6_A17 & !_LC7_A17
         # !_LC1_A17 &  _LC4_A23 &  _LC6_A17
         #  _LC1_A17 &  _LC4_A23 & !_LC6_A17 &  _LC7_A17;

-- Node name is '|FENPINQI:10|:5' = '|FENPINQI:10|COUT8' 
-- Equation name is '_LC4_A17', type is buried 
_LC4_A17 = DFFE( _EQ009, GLOBAL( F1KHZ),  VCC,  VCC,  VCC);
  _EQ009 = !_LC3_A17 &  _LC4_A17 &  _LC4_A23
         #  _LC3_A17 & !_LC4_A17 &  _LC4_A23;

-- Node name is '|FENPINQI:10|:4' = '|FENPINQI:10|COUT9' 
-- Equation name is '_LC8_A17', type is buried 
_LC8_A17 = DFFE( _EQ010, GLOBAL( F1KHZ),  VCC,  VCC,  VCC);
  _EQ010 = !_LC4_A17 &  _LC4_A23 &  _LC8_A17
         # !_LC3_A17 &  _LC4_A23 &  _LC8_A17
         #  _LC3_A17 &  _LC4_A17 &  _LC4_A23 & !_LC8_A17;

-- Node name is '|FENPINQI:10|LPM_ADD_SUB:161|addcore:adder|:87' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC2_A13', type is buried 
_LC2_A13 = LCELL( _EQ011);
  _EQ011 =  _LC3_A13 &  _LC4_A13 &  _LC5_A13;

-- Node name is '|FENPINQI:10|LPM_ADD_SUB:161|addcore:adder|:91' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC5_A23', type is buried 
_LC5_A23 = LCELL( _EQ012);
  _EQ012 =  _LC1_A23 &  _LC2_A13;

-- Node name is '|FENPINQI:10|LPM_ADD_SUB:161|addcore:adder|:99' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC1_A17', type is buried 
_LC1_A17 = LCELL( _EQ013);
  _EQ013 =  _LC1_A23 &  _LC2_A13 &  _LC2_A23 &  _LC5_A17;

-- Node name is '|FENPINQI:10|LPM_ADD_SUB:161|addcore:adder|:107' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC3_A17', type is buried 
_LC3_A17 = LCELL( _EQ014);
  _EQ014 =  _LC1_A17 &  _LC6_A17 &  _LC7_A17;

-- Node name is '|FENPINQI:10|:73' 
-- Equation name is '_LC4_A23', type is buried 
_LC4_A23 = LCELL( _EQ015);
  _EQ015 = !_LC2_A13 &  _LC3_A23
         # !_LC8_A17
         # !_LC2_A17;

-- Node name is '|FENPINQI:10|~95~1' 
-- Equation name is '_LC3_A23', type is buried 
-- synthesized logic cell 
_LC3_A23 = LCELL( _EQ016);
  _EQ016 = !_LC1_A23 & !_LC2_A23;

-- Node name is '|FENPINQI:10|~491~1' 
-- Equation name is '_LC2_A17', type is buried 
-- synthesized logic cell 
!_LC2_A17 = _LC2_A17~NOT;
_LC2_A17~NOT = LCELL( _EQ017);
  _EQ017 = !_LC4_A17
         # !_LC5_A17
         # !_LC6_A17
         # !_LC7_A17;

-- Node name is '|FENPINQI:10|~491~2' 
-- Equation name is '_LC7_A13', type is buried 
-- synthesized logic cell 
_LC7_A13 = LCELL( _EQ018);
  _EQ018 = !_LC1_A23 &  _LC2_A23 & !_LC5_A13 & !_LC8_A17;

-- Node name is '|FENPINQI:10|:491' 
-- Equation name is '_LC8_A13', type is buried 
_LC8_A13 = LCELL( _EQ019);
  _EQ019 =  _LC2_A17 &  _LC3_A13 &  _LC4_A13 &  _LC7_A13;

-- Node name is '|FENPINQI:10|:494' 
-- Equation name is '_LC1_A13', type is buried 
_LC1_A13 = LCELL( _EQ020);
  _EQ020 =  _LC1_A13 &  _LC6_A13
         #  _LC1_A13 & !_LC5_A13
         #  _LC8_A13;

-- Node name is '|FENPINQI:10|~496~1' 
-- Equation name is '_LC6_A13', type is buried 
-- synthesized logic cell 
_LC6_A13 = LCELL( _EQ021);
  _EQ021 =  _LC2_A23
         #  _LC1_A23
         # !_LC8_A17
         # !_LC2_A17;

-- Node name is '|TEST:8|:5' = '|TEST:8|DIV2CLK' 
-- Equation name is '_LC8_A24', type is buried 
_LC8_A24 = DFFE(!_LC8_A24,  _LC1_A13,  VCC,  VCC,  VCC);

-- Node name is '|TEST:8|~5~1' = '|TEST:8|DIV2CLK~1' 
-- Equation name is '_LC3_A24', type is buried 
-- synthesized logic cell 
_LC3_A24 = DFFE(!_LC3_A24,  _LC1_A13,  VCC,  VCC,  VCC);

-- Node name is '|TEST:8|:36' 
-- Equation name is '_LC1_A24', type is buried 
_LC1_A24 = LCELL( _EQ022);
  _EQ022 = !_LC1_A13 & !_LC8_A24;



Project Information             h:\eda\max+plus ii\besteve\test\fpqandtest.rpt

** COMPILATION SETTINGS & TIMES **

Processing Menu Commands
------------------------

Design Doctor                             = off

Logic Synthesis:

   Synthesis Type Used                    = Multi-Level

   Default Synthesis Style                = NORMAL

      Logic option settings in 'NORMAL' style for 'FLEX10K' family

      CARRY_CHAIN                         = ignore
      CARRY_CHAIN_LENGTH                  = 32
      CASCADE_CHAIN                       = ignore
      CASCADE_CHAIN_LENGTH                = 2
      DECOMPOSE_GATES                     = on
      DUPLICATE_LOGIC_EXTRACTION          = on
      MINIMIZATION                        = full
      MULTI_LEVEL_FACTORING               = on
      NOT_GATE_PUSH_BACK                  = on
      REDUCE_LOGIC                        = on
      REFACTORIZATION                     = on
      REGISTER_OPTIMIZATION               = on
      RESYNTHESIZE_NETWORK                = on
      SLOW_SLEW_RATE                      = off
      SUBFACTOR_EXTRACTION                = on
      IGNORE_SOFT_BUFFERS                 = on
      USE_LPM_FOR_AHDL_OPERATORS          = off

   Other logic synthesis settings:

      Automatic Global Clock              = on
      Automatic Global Clear              = on
      Automatic Global Preset             = on
      Automatic Global Output Enable      = on
      Automatic Fast I/O                  = off
      Automatic Register Packing          = off
      Automatic Open-Drain Pins           = on
      Automatic Implement in EAB          = off
      Optimize                            = 5

Default Timing Specifications: None

Cut All Bidir Feedback Timing Paths       = on
Cut All Clear & Preset Timing Paths       = on

Ignore Timing Assignments                 = off

Functional SNF Extractor                  = off

Linked SNF Extractor                      = off
Timing SNF Extractor                      = on
Optimize Timing SNF                       = off
Generate AHDL TDO File                    = off
Fitter Settings                           = NORMAL
Use Quartus Fitter                        = on
Smart Recompile                           = off
Total Recompile                           = off

Interfaces Menu Commands
------------------------

EDIF Netlist Writer                       = off
Verilog Netlist Writer                    = off
VHDL Netlist Writer                       = off

Compilation Times
-----------------

   Compiler Netlist Extractor             00:00:00
   Database Builder                       00:00:00
   Logic Synthesizer                      00:00:00
   Partitioner                            00:00:01
   Fitter                                 00:00:00
   Timing SNF Extractor                   00:00:00
   Assembler                              00:00:01
   --------------------------             --------
   Total Time                             00:00:02


Memory Allocated
-----------------

Peak memory allocated during compilation  = 30,372K