display.rpt

测频器

  _EQ009 =  COUTI0 &  COUTI1 & !COUTI2;

-- Node name is ':359' 
-- Equation name is '_LC5_A20', type is buried 
_LC5_A20 = LCELL( _EQ010);
  _EQ010 =  _LC4_A20 & !_LC5_A15
         #  A43 &  _LC5_A15;

-- Node name is ':366' 
-- Equation name is '_LC1_A18', type is buried 
_LC1_A18 = LCELL( _EQ011);
  _EQ011 = !COUTI0 &  COUTI1 & !COUTI2;

-- Node name is ':369' 
-- Equation name is '_LC7_A20', type is buried 
_LC7_A20 = LCELL( _EQ012);
  _EQ012 = !_LC1_A18 &  _LC5_A20
         #  A33 &  _LC1_A18;

-- Node name is ':376' 
-- Equation name is '_LC3_A15', type is buried 
_LC3_A15 = LCELL( _EQ013);
  _EQ013 =  COUTI0 & !COUTI1 & !COUTI2;

-- Node name is ':379' 
-- Equation name is '_LC8_A20', type is buried 
_LC8_A20 = LCELL( _EQ014);
  _EQ014 = !_LC3_A15 &  _LC7_A20
         #  A23 &  _LC3_A15;

-- Node name is ':386' 
-- Equation name is '_LC2_A15', type is buried 
_LC2_A15 = LCELL( _EQ015);
  _EQ015 = !COUTI0 & !COUTI1 & !COUTI2;

-- Node name is ':389' 
-- Equation name is '_LC6_A20', type is buried 
_LC6_A20 = LCELL( _EQ016);
  _EQ016 = !_LC2_A15 &  _LC8_A20
         #  A13 &  _LC2_A15;

-- Node name is ':395' 
-- Equation name is '_LC1_A13', type is buried 
_LC1_A13 = LCELL( _EQ017);
  _EQ017 =  A82 & !_LC7_A15
         #  A72 &  _LC7_A15;

-- Node name is ':398' 
-- Equation name is '_LC2_A23', type is buried 
_LC2_A23 = LCELL( _EQ018);
  _EQ018 =  A62 &  _LC8_A15
         #  _LC1_A13 & !_LC8_A15;

-- Node name is ':401' 
-- Equation name is '_LC3_A23', type is buried 
_LC3_A23 = LCELL( _EQ019);
  _EQ019 =  _LC2_A23 & !_LC6_A15
         #  A52 &  _LC6_A15;

-- Node name is ':404' 
-- Equation name is '_LC6_A23', type is buried 
_LC6_A23 = LCELL( _EQ020);
  _EQ020 =  _LC3_A23 & !_LC5_A15
         #  A42 &  _LC5_A15;

-- Node name is ':407' 
-- Equation name is '_LC7_A23', type is buried 
_LC7_A23 = LCELL( _EQ021);
  _EQ021 = !_LC1_A18 &  _LC6_A23
         #  A32 &  _LC1_A18;

-- Node name is ':410' 
-- Equation name is '_LC8_A23', type is buried 
_LC8_A23 = LCELL( _EQ022);
  _EQ022 = !_LC3_A15 &  _LC7_A23
         #  A22 &  _LC3_A15;

-- Node name is ':413' 
-- Equation name is '_LC4_A23', type is buried 
_LC4_A23 = LCELL( _EQ023);
  _EQ023 = !_LC2_A15 &  _LC8_A23
         #  A12 &  _LC2_A15;

-- Node name is ':419' 
-- Equation name is '_LC3_A13', type is buried 
_LC3_A13 = LCELL( _EQ024);
  _EQ024 =  A81 & !_LC7_A15
         #  A71 &  _LC7_A15;

-- Node name is ':422' 
-- Equation name is '_LC4_A13', type is buried 
_LC4_A13 = LCELL( _EQ025);
  _EQ025 =  A61 &  _LC8_A15
         #  _LC3_A13 & !_LC8_A15;

-- Node name is ':425' 
-- Equation name is '_LC5_A13', type is buried 
_LC5_A13 = LCELL( _EQ026);
  _EQ026 =  _LC4_A13 & !_LC6_A15
         #  A51 &  _LC6_A15;

-- Node name is ':428' 
-- Equation name is '_LC6_A13', type is buried 
_LC6_A13 = LCELL( _EQ027);
  _EQ027 =  _LC5_A13 & !_LC5_A15
         #  A41 &  _LC5_A15;

-- Node name is ':431' 
-- Equation name is '_LC2_A13', type is buried 
_LC2_A13 = LCELL( _EQ028);
  _EQ028 = !_LC1_A18 &  _LC6_A13
         #  A31 &  _LC1_A18;

-- Node name is ':434' 
-- Equation name is '_LC1_A23', type is buried 
_LC1_A23 = LCELL( _EQ029);
  _EQ029 =  _LC2_A13 & !_LC3_A15
         #  A21 &  _LC3_A15;

-- Node name is ':437' 
-- Equation name is '_LC5_A23', type is buried 
_LC5_A23 = LCELL( _EQ030);
  _EQ030 =  _LC1_A23 & !_LC2_A15
         #  A11 &  _LC2_A15;

-- Node name is ':443' 
-- Equation name is '_LC1_A20', type is buried 
_LC1_A20 = LCELL( _EQ031);
  _EQ031 =  A80 & !_LC7_A15
         #  A70 &  _LC7_A15;

-- Node name is ':446' 
-- Equation name is '_LC3_A18', type is buried 
_LC3_A18 = LCELL( _EQ032);
  _EQ032 =  A60 &  _LC8_A15
         #  _LC1_A20 & !_LC8_A15;

-- Node name is ':449' 
-- Equation name is '_LC4_A18', type is buried 
_LC4_A18 = LCELL( _EQ033);
  _EQ033 =  _LC3_A18 & !_LC6_A15
         #  A50 &  _LC6_A15;

-- Node name is ':452' 
-- Equation name is '_LC5_A18', type is buried 
_LC5_A18 = LCELL( _EQ034);
  _EQ034 =  _LC4_A18 & !_LC5_A15
         #  A40 &  _LC5_A15;

-- Node name is ':455' 
-- Equation name is '_LC6_A18', type is buried 
_LC6_A18 = LCELL( _EQ035);
  _EQ035 = !_LC1_A18 &  _LC5_A18
         #  A30 &  _LC1_A18;

-- Node name is ':458' 
-- Equation name is '_LC7_A18', type is buried 
_LC7_A18 = LCELL( _EQ036);
  _EQ036 = !_LC3_A15 &  _LC6_A18
         #  A20 &  _LC3_A15;

-- Node name is ':461' 
-- Equation name is '_LC2_A18', type is buried 
_LC2_A18 = LCELL( _EQ037);
  _EQ037 = !_LC2_A15 &  _LC7_A18
         #  A10 &  _LC2_A15;



Project Information                h:\eda\max_pl~1\besteve\quzheng\display.rpt

** COMPILATION SETTINGS & TIMES **

Processing Menu Commands
------------------------

Design Doctor                             = off

Logic Synthesis:

   Synthesis Type Used                    = Multi-Level

   Default Synthesis Style                = NORMAL

      Logic option settings in 'NORMAL' style for 'FLEX10K' family

      CARRY_CHAIN                         = ignore
      CARRY_CHAIN_LENGTH                  = 32
      CASCADE_CHAIN                       = ignore
      CASCADE_CHAIN_LENGTH                = 2
      DECOMPOSE_GATES                     = on
      DUPLICATE_LOGIC_EXTRACTION          = on
      MINIMIZATION                        = full
      MULTI_LEVEL_FACTORING               = on
      NOT_GATE_PUSH_BACK                  = on
      REDUCE_LOGIC                        = on
      REFACTORIZATION                     = on
      REGISTER_OPTIMIZATION               = on
      RESYNTHESIZE_NETWORK                = on
      SLOW_SLEW_RATE                      = off
      SUBFACTOR_EXTRACTION                = on
      IGNORE_SOFT_BUFFERS                 = on
      USE_LPM_FOR_AHDL_OPERATORS          = off

   Other logic synthesis settings:

      Automatic Global Clock              = on
      Automatic Global Clear              = on
      Automatic Global Preset             = on
      Automatic Global Output Enable      = on
      Automatic Fast I/O                  = off
      Automatic Register Packing          = off
      Automatic Open-Drain Pins           = on
      Automatic Implement in EAB          = off
      Optimize                            = 5

Default Timing Specifications: None

Cut All Bidir Feedback Timing Paths       = on
Cut All Clear & Preset Timing Paths       = on

Ignore Timing Assignments                 = off

Functional SNF Extractor                  = off

Linked SNF Extractor                      = off
Timing SNF Extractor                      = on
Optimize Timing SNF                       = off
Generate AHDL TDO File                    = off
Fitter Settings                           = NORMAL
Use Quartus Fitter                        = on
Smart Recompile                           = off
Total Recompile                           = off

Interfaces Menu Commands
------------------------

EDIF Netlist Writer                       = off
Verilog Netlist Writer                    = off
VHDL Netlist Writer                       = off

Compilation Times
-----------------

   Compiler Netlist Extractor             00:00:00
   Database Builder                       00:00:00
   Logic Synthesizer                      00:00:00
   Partitioner                            00:00:01
   Fitter                                 00:00:01
   Timing SNF Extractor                   00:00:00
   Assembler                              00:00:00
   --------------------------             --------
   Total Time                             00:00:02


Memory Allocated
-----------------

Peak memory allocated during compilation  = 10,590K