📄 display.rpt
字号:
display
** OUTPUTS **
Fed By Fed By Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
61 - - C -- OUTPUT 0 1 0 0 DISPLAYOUT0
65 - - B -- OUTPUT 0 1 0 0 DISPLAYOUT1
60 - - C -- OUTPUT 0 1 0 0 DISPLAYOUT2
58 - - C -- OUTPUT 0 1 0 0 DISPLAYOUT3
70 - - A -- OUTPUT 0 1 0 0 KEY0
71 - - A -- OUTPUT 0 1 0 0 KEY1
73 - - A -- OUTPUT 0 1 0 0 KEY2
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
Device-Specific Information: h:\eda\max_pl~1\besteve\quzheng\display.rpt
display
** BURIED LOGIC **
Fan-In Fan-Out
IOC LC EC Row Col Primitive Code INP FBK OUT FBK Name
- 1 - A 15 DFFE + 0 2 1 7 COUTI2 (:41)
- 4 - A 15 DFFE + 0 1 1 8 COUTI1 (:42)
- 8 - A 18 DFFE + 0 0 1 9 COUTI0 (:43)
- 7 - A 15 AND2 0 3 0 4 :326
- 2 - A 20 OR2 2 1 0 1 :329
- 8 - A 15 OR2 ! 0 3 0 4 :336
- 3 - A 20 OR2 1 2 0 1 :339
- 6 - A 15 AND2 0 3 0 4 :346
- 4 - A 20 OR2 1 2 0 1 :349
- 5 - A 15 AND2 0 3 0 4 :356
- 5 - A 20 OR2 1 2 0 1 :359
- 1 - A 18 AND2 0 3 0 4 :366
- 7 - A 20 OR2 1 2 0 1 :369
- 3 - A 15 AND2 0 3 0 4 :376
- 8 - A 20 OR2 1 2 0 1 :379
- 2 - A 15 AND2 0 3 0 4 :386
- 6 - A 20 OR2 1 2 1 0 :389
- 1 - A 13 OR2 2 1 0 1 :395
- 2 - A 23 OR2 1 2 0 1 :398
- 3 - A 23 OR2 1 2 0 1 :401
- 6 - A 23 OR2 1 2 0 1 :404
- 7 - A 23 OR2 1 2 0 1 :407
- 8 - A 23 OR2 1 2 0 1 :410
- 4 - A 23 OR2 1 2 1 0 :413
- 3 - A 13 OR2 2 1 0 1 :419
- 4 - A 13 OR2 1 2 0 1 :422
- 5 - A 13 OR2 1 2 0 1 :425
- 6 - A 13 OR2 1 2 0 1 :428
- 2 - A 13 OR2 1 2 0 1 :431
- 1 - A 23 OR2 1 2 0 1 :434
- 5 - A 23 OR2 1 2 1 0 :437
- 1 - A 20 OR2 2 1 0 1 :443
- 3 - A 18 OR2 1 2 0 1 :446
- 4 - A 18 OR2 1 2 0 1 :449
- 5 - A 18 OR2 1 2 0 1 :452
- 6 - A 18 OR2 1 2 0 1 :455
- 7 - A 18 OR2 1 2 0 1 :458
- 2 - A 18 OR2 1 2 1 0 :461
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
p = Packed register
Device-Specific Information: h:\eda\max_pl~1\besteve\quzheng\display.rpt
display
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 21/ 96( 21%) 0/ 48( 0%) 20/ 48( 41%) 6/16( 37%) 3/16( 18%) 0/16( 0%)
B: 0/ 96( 0%) 0/ 48( 0%) 1/ 48( 2%) 0/16( 0%) 1/16( 6%) 0/16( 0%)
C: 0/ 96( 0%) 0/ 48( 0%) 3/ 48( 6%) 0/16( 0%) 3/16( 18%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
02: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
03: 2/24( 8%) 2/4( 50%) 0/4( 0%) 0/4( 0%)
04: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
05: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
06: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
07: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
10: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
11: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
13: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
14: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
15: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
16: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
17: 2/24( 8%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
18: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
19: 2/24( 8%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
20: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
21: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
22: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
23: 3/24( 12%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
24: 2/24( 8%) 2/4( 50%) 0/4( 0%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: h:\eda\max_pl~1\besteve\quzheng\display.rpt
display
** CLOCK SIGNALS **
Type Fan-out Name
INPUT 3 CLK
Device-Specific Information: h:\eda\max_pl~1\besteve\quzheng\display.rpt
display
** EQUATIONS **
A10 : INPUT;
A11 : INPUT;
A12 : INPUT;
A13 : INPUT;
A20 : INPUT;
A21 : INPUT;
A22 : INPUT;
A23 : INPUT;
A30 : INPUT;
A31 : INPUT;
A32 : INPUT;
A33 : INPUT;
A40 : INPUT;
A41 : INPUT;
A42 : INPUT;
A43 : INPUT;
A50 : INPUT;
A51 : INPUT;
A52 : INPUT;
A53 : INPUT;
A60 : INPUT;
A61 : INPUT;
A62 : INPUT;
A63 : INPUT;
A70 : INPUT;
A71 : INPUT;
A72 : INPUT;
A73 : INPUT;
A80 : INPUT;
A81 : INPUT;
A82 : INPUT;
A83 : INPUT;
CLK : INPUT;
-- Node name is ':43' = 'COUTI0'
-- Equation name is 'COUTI0', location is LC8_A18, type is buried.
COUTI0 = DFFE(!COUTI0, GLOBAL( CLK), VCC, VCC, VCC);
-- Node name is ':42' = 'COUTI1'
-- Equation name is 'COUTI1', location is LC4_A15, type is buried.
COUTI1 = DFFE( _EQ001, GLOBAL( CLK), VCC, VCC, VCC);
_EQ001 = !COUTI0 & COUTI1
# COUTI0 & !COUTI1;
-- Node name is ':41' = 'COUTI2'
-- Equation name is 'COUTI2', location is LC1_A15, type is buried.
COUTI2 = DFFE( _EQ002, GLOBAL( CLK), VCC, VCC, VCC);
_EQ002 = COUTI0 & COUTI1 & !COUTI2
# !COUTI1 & COUTI2
# !COUTI0 & COUTI2;
-- Node name is 'DISPLAYOUT0'
-- Equation name is 'DISPLAYOUT0', type is output
DISPLAYOUT0 = _LC2_A18;
-- Node name is 'DISPLAYOUT1'
-- Equation name is 'DISPLAYOUT1', type is output
DISPLAYOUT1 = _LC5_A23;
-- Node name is 'DISPLAYOUT2'
-- Equation name is 'DISPLAYOUT2', type is output
DISPLAYOUT2 = _LC4_A23;
-- Node name is 'DISPLAYOUT3'
-- Equation name is 'DISPLAYOUT3', type is output
DISPLAYOUT3 = _LC6_A20;
-- Node name is 'KEY0'
-- Equation name is 'KEY0', type is output
KEY0 = COUTI0;
-- Node name is 'KEY1'
-- Equation name is 'KEY1', type is output
KEY1 = COUTI1;
-- Node name is 'KEY2'
-- Equation name is 'KEY2', type is output
KEY2 = COUTI2;
-- Node name is ':326'
-- Equation name is '_LC7_A15', type is buried
_LC7_A15 = LCELL( _EQ003);
_EQ003 = !COUTI0 & COUTI1 & COUTI2;
-- Node name is ':329'
-- Equation name is '_LC2_A20', type is buried
_LC2_A20 = LCELL( _EQ004);
_EQ004 = A83 & !_LC7_A15
# A73 & _LC7_A15;
-- Node name is ':336'
-- Equation name is '_LC8_A15', type is buried
!_LC8_A15 = _LC8_A15~NOT;
_LC8_A15~NOT = LCELL( _EQ005);
_EQ005 = COUTI1
# !COUTI0
# !COUTI2;
-- Node name is ':339'
-- Equation name is '_LC3_A20', type is buried
_LC3_A20 = LCELL( _EQ006);
_EQ006 = A63 & _LC8_A15
# _LC2_A20 & !_LC8_A15;
-- Node name is ':346'
-- Equation name is '_LC6_A15', type is buried
_LC6_A15 = LCELL( _EQ007);
_EQ007 = !COUTI0 & !COUTI1 & COUTI2;
-- Node name is ':349'
-- Equation name is '_LC4_A20', type is buried
_LC4_A20 = LCELL( _EQ008);
_EQ008 = _LC3_A20 & !_LC6_A15
# A53 & _LC6_A15;
-- Node name is ':356'
-- Equation name is '_LC5_A15', type is buried
_LC5_A15 = LCELL( _EQ009);
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