📄 jpqnotfpq.rpt
字号:
1 - - - -- INPUT G 0 0 0 0 FIN
43 - - - -- INPUT G 0 0 0 1 F1KHZ
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
G = Global Source. Fan-out destinations counted here do not include destinations
that are driven using global routing resources. Refer to the Auto Global Signals,
Clock Signals, Clear Signals, Synchronous Load Signals, and Synchronous Clear Signals
Sections of this Report File for information on which signals' fan-outs are used as
Clock, Clear, Preset, Output Enable, and synchronous Load signals.
Device-Specific Information: h:\eda\max_pl~1\besteve\quzheng\jpqnotfpq.rpt
jpqnotfpq
** OUTPUTS **
Fed By Fed By Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
71 - - A -- OUTPUT 0 1 0 0 COUTT
21 - - B -- OUTPUT 0 1 0 0 DISBLAY0
64 - - B -- OUTPUT 0 1 0 0 DISBLAY1
25 - - B -- OUTPUT 0 1 0 0 DISBLAY2
65 - - B -- OUTPUT 0 1 0 0 DISBLAY3
23 - - B -- OUTPUT 0 1 0 0 DISBLAY4
22 - - B -- OUTPUT 0 1 0 0 DISBLAY5
24 - - B -- OUTPUT 0 1 0 0 DISBLAY6
18 - - A -- OUTPUT 0 1 0 0 KEY0
16 - - A -- OUTPUT 0 1 0 0 KEY1
17 - - A -- OUTPUT 0 1 0 0 KEY2
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
Device-Specific Information: h:\eda\max_pl~1\besteve\quzheng\jpqnotfpq.rpt
jpqnotfpq
** BURIED LOGIC **
Fan-In Fan-Out
IOC LC EC Row Col Primitive Code INP FBK OUT FBK Name
- 7 - A 03 AND2 0 2 0 1 |CNT10:13|LPM_ADD_SUB:52|addcore:adder|:55
- 3 - A 03 OR2 0 4 0 1 |CNT10:13|LPM_ADD_SUB:52|addcore:adder|:69
- 4 - A 03 DFFE + 0 4 0 4 |CNT10:13|CQI3 (|CNT10:13|:11)
- 2 - A 03 DFFE + 0 4 0 4 |CNT10:13|CQI2 (|CNT10:13|:12)
- 5 - A 03 DFFE + 0 4 0 5 |CNT10:13|CQI1 (|CNT10:13|:13)
- 8 - A 03 DFFE + 0 3 0 6 |CNT10:13|CQI0 (|CNT10:13|:14)
- 6 - A 03 OR2 0 4 0 4 |CNT10:13|:31
- 1 - A 03 AND2 0 4 0 4 |CNT10:13|:117
- 8 - A 12 AND2 0 2 0 1 |CNT10:14|LPM_ADD_SUB:52|addcore:adder|:55
- 6 - A 12 OR2 0 4 0 1 |CNT10:14|LPM_ADD_SUB:52|addcore:adder|:69
- 3 - A 12 DFFE 0 5 0 4 |CNT10:14|CQI3 (|CNT10:14|:11)
- 4 - A 12 DFFE 0 5 0 4 |CNT10:14|CQI2 (|CNT10:14|:12)
- 1 - A 12 DFFE 0 5 0 5 |CNT10:14|CQI1 (|CNT10:14|:13)
- 5 - A 12 DFFE 0 4 0 6 |CNT10:14|CQI0 (|CNT10:14|:14)
- 7 - A 12 OR2 0 4 0 4 |CNT10:14|:31
- 2 - A 12 AND2 0 4 0 4 |CNT10:14|:117
- 6 - A 11 AND2 0 2 0 1 |CNT10:15|LPM_ADD_SUB:52|addcore:adder|:55
- 8 - A 11 OR2 0 4 0 1 |CNT10:15|LPM_ADD_SUB:52|addcore:adder|:69
- 2 - A 11 DFFE 0 5 0 4 |CNT10:15|CQI3 (|CNT10:15|:11)
- 4 - A 11 DFFE 0 5 0 4 |CNT10:15|CQI2 (|CNT10:15|:12)
- 5 - A 11 DFFE 0 5 0 5 |CNT10:15|CQI1 (|CNT10:15|:13)
- 1 - A 11 DFFE 0 4 0 6 |CNT10:15|CQI0 (|CNT10:15|:14)
- 7 - A 11 OR2 0 4 0 4 |CNT10:15|:31
- 3 - A 11 AND2 0 4 0 4 |CNT10:15|:117
- 7 - A 21 AND2 0 2 0 1 |CNT10:16|LPM_ADD_SUB:52|addcore:adder|:55
- 8 - A 21 OR2 0 4 0 1 |CNT10:16|LPM_ADD_SUB:52|addcore:adder|:69
- 1 - A 21 DFFE 0 5 0 4 |CNT10:16|CQI3 (|CNT10:16|:11)
- 2 - A 21 DFFE 0 5 0 4 |CNT10:16|CQI2 (|CNT10:16|:12)
- 3 - A 21 DFFE 0 5 0 5 |CNT10:16|CQI1 (|CNT10:16|:13)
- 4 - A 21 DFFE 0 4 0 6 |CNT10:16|CQI0 (|CNT10:16|:14)
- 6 - A 21 OR2 0 4 0 4 |CNT10:16|:31
- 5 - A 21 AND2 0 4 0 4 |CNT10:16|:117
- 7 - A 18 AND2 0 2 0 1 |CNT10:17|LPM_ADD_SUB:52|addcore:adder|:55
- 8 - A 18 OR2 0 4 0 1 |CNT10:17|LPM_ADD_SUB:52|addcore:adder|:69
- 4 - A 18 DFFE 0 5 0 4 |CNT10:17|CQI3 (|CNT10:17|:11)
- 5 - A 18 DFFE 0 5 0 4 |CNT10:17|CQI2 (|CNT10:17|:12)
- 2 - A 18 DFFE 0 5 0 5 |CNT10:17|CQI1 (|CNT10:17|:13)
- 3 - A 18 DFFE 0 4 0 6 |CNT10:17|CQI0 (|CNT10:17|:14)
- 6 - A 18 OR2 0 4 0 4 |CNT10:17|:31
- 1 - A 18 AND2 0 4 0 4 |CNT10:17|:117
- 7 - A 19 AND2 0 2 0 1 |CNT10:18|LPM_ADD_SUB:52|addcore:adder|:55
- 8 - A 19 OR2 0 4 0 1 |CNT10:18|LPM_ADD_SUB:52|addcore:adder|:69
- 2 - A 19 DFFE 0 5 0 4 |CNT10:18|CQI3 (|CNT10:18|:11)
- 5 - A 19 DFFE 0 5 0 4 |CNT10:18|CQI2 (|CNT10:18|:12)
- 3 - A 19 DFFE 0 5 0 5 |CNT10:18|CQI1 (|CNT10:18|:13)
- 1 - A 19 DFFE 0 4 0 6 |CNT10:18|CQI0 (|CNT10:18|:14)
- 6 - A 19 OR2 0 4 0 4 |CNT10:18|:31
- 4 - A 19 AND2 0 4 0 4 |CNT10:18|:117
- 7 - A 15 AND2 0 2 0 1 |CNT10:19|LPM_ADD_SUB:52|addcore:adder|:55
- 8 - A 15 OR2 0 4 0 1 |CNT10:19|LPM_ADD_SUB:52|addcore:adder|:69
- 3 - A 15 DFFE 0 5 0 4 |CNT10:19|CQI3 (|CNT10:19|:11)
- 4 - A 15 DFFE 0 5 0 4 |CNT10:19|CQI2 (|CNT10:19|:12)
- 5 - A 15 DFFE 0 5 0 5 |CNT10:19|CQI1 (|CNT10:19|:13)
- 2 - A 15 DFFE 0 4 0 6 |CNT10:19|CQI0 (|CNT10:19|:14)
- 6 - A 15 OR2 0 4 0 4 |CNT10:19|:31
- 1 - A 15 AND2 0 4 0 4 |CNT10:19|:117
- 6 - A 20 AND2 0 2 0 1 |CNT10:20|LPM_ADD_SUB:52|addcore:adder|:55
- 8 - A 20 OR2 0 4 0 1 |CNT10:20|LPM_ADD_SUB:52|addcore:adder|:69
- 3 - A 20 DFFE 0 5 0 4 |CNT10:20|CQI3 (|CNT10:20|:11)
- 1 - A 20 DFFE 0 5 0 4 |CNT10:20|CQI2 (|CNT10:20|:12)
- 7 - A 20 DFFE 0 5 0 5 |CNT10:20|CQI1 (|CNT10:20|:13)
- 2 - A 20 DFFE 0 4 0 6 |CNT10:20|CQI0 (|CNT10:20|:14)
- 5 - A 20 OR2 0 4 0 4 |CNT10:20|:31
- 4 - A 20 AND2 0 4 1 0 |CNT10:20|:117
- 1 - B 02 OR2 s ! 0 3 0 1 |DECL7S:1|~251~1
- 7 - B 02 AND2 s ! 0 3 0 7 |DECL7S:1|~263~1
- 4 - B 03 AND2 0 2 0 1 |DECL7S:1|:263
- 7 - B 03 OR2 0 4 0 1 |DECL7S:1|:280
- 3 - B 02 AND2 s 0 3 0 6 |DECL7S:1|~287~1
- 2 - B 10 OR2 ! 0 2 0 1 |DECL7S:1|:299
- 3 - B 03 AND2 0 2 0 1 |DECL7S:1|:311
- 6 - B 02 AND2 s 0 3 0 4 |DECL7S:1|~323~1
- 2 - B 03 OR2 ! 0 2 0 1 |DECL7S:1|:323
- 1 - B 05 OR2 s 0 3 0 4 |DECL7S:1|~326~1
- 5 - B 02 OR2 s 0 3 0 7 |DECL7S:1|~347~1
- 8 - B 10 AND2 0 2 0 1 |DECL7S:1|:347
- 6 - B 03 OR2 0 4 1 1 |DECL7S:1|:350
- 1 - B 03 AND2 s ! 0 1 0 2 |DECL7S:1|~352~1
- 2 - B 02 OR2 0 4 0 1 |DECL7S:1|:367
- 1 - B 10 OR2 0 4 1 1 |DECL7S:1|:383
- 5 - B 10 OR2 s ! 0 3 0 2 |DECL7S:1|~385~1
- 7 - B 05 OR2 0 4 0 1 |DECL7S:1|:398
- 8 - B 05 OR2 0 4 0 1 |DECL7S:1|:410
- 4 - B 05 OR2 0 3 1 1 |DECL7S:1|:416
- 3 - B 05 OR2 0 4 0 1 |DECL7S:1|:433
- 6 - B 05 OR2 0 4 0 1 |DECL7S:1|:442
- 5 - B 05 OR2 0 4 1 1 |DECL7S:1|:449
- 4 - B 02 OR2 s 0 3 0 2 |DECL7S:1|~473~1
- 2 - B 05 OR2 s 0 3 0 3 |DECL7S:1|~473~2
- 5 - B 03 OR2 s 0 4 0 1 |DECL7S:1|~473~3
- 8 - B 03 OR2 0 3 1 0 |DECL7S:1|:482
- 8 - B 02 AND2 s 0 3 0 5 |DECL7S:1|~494~1
- 7 - B 10 OR2 s 0 4 0 1 |DECL7S:1|~515~1
- 6 - B 10 OR2 0 3 1 0 |DECL7S:1|:515
- 3 - B 10 OR2 0 4 0 1 |DECL7S:1|:541
- 1 - B 09 AND2 s 0 1 0 4 |DECL7S:1|~542~1
- 4 - B 10 OR2 0 4 1 1 |DECL7S:1|:548
- 2 - A 04 DFFE + 0 2 1 7 |DISPLAY:69|COUTI2 (|DISPLAY:69|:41)
- 1 - A 04 DFFE + 0 1 1 8 |DISPLAY:69|COUTI1 (|DISPLAY:69|:42)
- 5 - A 01 DFFE + 0 0 1 9 |DISPLAY:69|COUTI0 (|DISPLAY:69|:43)
- 7 - A 04 AND2 0 3 0 4 |DISPLAY:69|:326
- 7 - A 16 OR2 ! 0 3 0 1 |DISPLAY:69|:329
- 6 - A 04 OR2 ! 0 3 0 4 |DISPLAY:69|:336
- 1 - A 16 OR2 ! 0 3 0 1 |DISPLAY:69|:339
- 3 - A 04 AND2 0 3 0 5 |DISPLAY:69|:346
- 6 - A 05 OR2 ! 0 3 0 1 |DISPLAY:69|:349
- 4 - A 04 AND2 0 3 0 4 |DISPLAY:69|:356
- 7 - A 05 OR2 ! 0 3 0 1 |DISPLAY:69|:359
- 8 - A 04 AND2 0 3 0 4 |DISPLAY:69|:366
- 8 - A 05 OR2 ! 0 3 0 1 |DISPLAY:69|:369
- 1 - A 01 AND2 0 3 0 5 |DISPLAY:69|:376
- 1 - A 05 OR2 ! 0 3 0 1 |DISPLAY:69|:379
- 5 - A 04 AND2 0 3 0 4 |DISPLAY:69|:386
- 2 - A 07 OR2 ! 0 3 0 6 |DISPLAY:69|:389
- 5 - A 23 OR2 0 3 0 1 |DISPLAY:69|:395
- 6 - A 23 OR2 0 3 0 1 |DISPLAY:69|:398
- 8 - A 23 OR2 0 3 0 1 |DISPLAY:69|:401
- 1 - A 23 OR2 0 3 0 1 |DISPLAY:69|:404
- 3 - A 08 OR2 0 3 0 1 |DISPLAY:69|:407
- 5 - A 08 OR2 0 3 0 1 |DISPLAY:69|:410
- 1 - A 08 OR2 0 3 0 6 |DISPLAY:69|:413
- 4 - A 13 OR2 0 3 0 1 |DISPLAY:69|:419
- 5 - A 13 OR2 0 3 0 1 |DISPLAY:69|:422
- 7 - A 13 OR2 0 3 0 1 |DISPLAY:69|:425
- 1 - A 13 OR2 0 3 0 1 |DISPLAY:69|:428
- 5 - A 07 OR2 0 3 0 1 |DISPLAY:69|:431
- 7 - A 07 OR2 0 3 0 1 |DISPLAY:69|:434
- 1 - A 07 OR2 0 3 0 6 |DISPLAY:69|:437
- 2 - A 16 OR2 0 3 0 1 |DISPLAY:69|:443
- 6 - A 17 AND2 0 2 0 1 |DISPLAY:69|:450
- 2 - A 17 OR2 0 4 0 1 |DISPLAY:69|:451
- 4 - A 17 OR2 0 4 0 1 |DISPLAY:69|:452
- 7 - A 01 AND2 0 2 0 1 |DISPLAY:69|:459
- 4 - A 01 OR2 0 4 0 1 |DISPLAY:69|:460
- 2 - A 01 OR2 0 4 0 19 |DISPLAY:69|:461
- 3 - A 07 DFFE 0 2 0 1 |REG4B:2|:6
- 6 - A 08 DFFE 0 2 0 1 |REG4B:2|:8
- 8 - A 07 DFFE 0 2 0 1 |REG4B:2|:10
- 8 - A 01 DFFE 0 2 0 1 |REG4B:2|:12
- 2 - A 05 DFFE 0 2 0 1 |REG4B:21|:6
- 4 - A 08 DFFE 0 2 0 1 |REG4B:21|:8
- 6 - A 07 DFFE 0 2 0 1 |REG4B:21|:10
- 6 - A 01 DFFE 0 2 0 1 |REG4B:21|:12
- 3 - A 05 DFFE 0 2 0 1 |REG4B:22|:6
- 2 - A 08 DFFE 0 2 0 1 |REG4B:22|:8
- 4 - A 07 DFFE 0 2 0 1 |REG4B:22|:10
- 3 - A 01 DFFE 0 2 0 1 |REG4B:22|:12
- 4 - A 05 DFFE 0 2 0 1 |REG4B:23|:6
- 1 - A 24 DFFE 0 2 0 1 |REG4B:23|:8
- 8 - A 13 DFFE 0 2 0 1 |REG4B:23|:10
- 7 - A 17 DFFE 0 2 0 1 |REG4B:23|:12
- 5 - A 05 DFFE 0 2 0 1 |REG4B:24|:6
- 7 - A 23 DFFE 0 2 0 1 |REG4B:24|:8
- 6 - A 13 DFFE 0 2 0 1 |REG4B:24|:10
- 3 - A 17 DFFE 0 2 0 1 |REG4B:24|:12
- 8 - A 16 DFFE 0 2 0 1 |REG4B:25|:6
- 2 - A 23 DFFE 0 2 0 1 |REG4B:25|:8
- 1 - A 14 DFFE 0 2 0 1 |REG4B:25|:10
- 1 - A 17 DFFE 0 2 0 1 |REG4B:25|:12
- 5 - A 16 DFFE 0 2 0 1 |REG4B:26|:6
- 4 - A 23 DFFE 0 2 0 1 |REG4B:26|:8
- 3 - A 13 DFFE 0 2 0 1 |REG4B:26|:10
- 4 - A 16 DFFE 0 2 0 1 |REG4B:26|:12
- 6 - A 16 DFFE 0 2 0 1 |REG4B:27|:6
- 3 - A 23 DFFE 0 2 0 1 |REG4B:27|:8
- 2 - A 13 DFFE 0 2 0 1 |REG4B:27|:10
- 3 - A 16 DFFE 0 2 0 1 |REG4B:27|:12
- 5 - A 17 DFFE + 0 0 0 65 |TEST:3|DIV2CLK (|TEST:3|:5)
- 1 - A 10 OR2 ! 1 1 0 32 |TEST:3|:36
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
p = Packed register
Device-Specific Information: h:\eda\max_pl~1\besteve\quzheng\jpqnotfpq.rpt
jpqnotfpq
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 23/ 96( 23%) 19/ 48( 39%) 19/ 48( 39%) 0/16( 0%) 4/16( 25%) 0/16( 0%)
B: 4/ 96( 4%) 18/ 48( 37%) 0/ 48( 0%) 0/16( 0%) 7/16( 43%) 0/16( 0%)
C: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
02: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
03: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
04: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
05: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
06: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
07: 2/24( 8%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
08: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
10: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
14: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
15: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
16: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
17: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
18: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
19: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
20: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
21: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
22: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
23: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
24: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: h:\eda\max_pl~1\besteve\quzheng\jpqnotfpq.rpt
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