test.vhd

来自「测频器」· VHDL 代码 · 共 29 行

--Author    	: 屈峥 2002081212
--File Name 	: test.vhd
--Objective 	: 测频控制器
--
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY TEST IS
   PORT ( CLKK : IN STD_LOGIC; -- 1Hz 
          CNT_EN,RST_CNT,LOAD : OUT STD_LOGIC);
END TEST;
ARCHITECTURE BEHAV OF TEST IS
   SIGNAL DIV2CLK : STD_LOGIC;
   BEGIN
      PROCESS (CLKK)
      BEGIN
      IF CLKK'EVENT AND CLKK = '1' THEN DIV2CLK <= NOT DIV2CLK;
      END IF;
   END PROCESS;
   PROCESS (CLKK,DIV2CLK)
      BEGIN
      IF CLKK  = '0' AND DIV2CLK = '0' THEN RST_CNT <= '1';
         ELSE RST_CNT <= '0';
      END IF;
   END PROCESS;
      LOAD <= NOT DIV2CLK;
      CNT_EN <= DIV2CLK;
END BEHAV;