📄 fenpinqi.rpt
字号:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
B: 0/ 96( 0%) 0/ 48( 0%) 9/ 48( 18%) 0/16( 0%) 2/16( 12%) 0/16( 0%)
C: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
02: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
03: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
04: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
05: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
06: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
07: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
10: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
14: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
15: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
16: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
17: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
18: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
19: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
20: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
21: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
22: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
23: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
24: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: g:\eda\max_pl~1\besteve\quzheng\fenpinqi.rpt
fenpinqi
** CLOCK SIGNALS **
Type Fan-out Name
INPUT 11 F1KHZ
Device-Specific Information: g:\eda\max_pl~1\besteve\quzheng\fenpinqi.rpt
fenpinqi
** EQUATIONS **
F1KHZ : INPUT;
-- Node name is 'CLK'
-- Equation name is 'CLK', type is output
CLK = _LC1_B21;
-- Node name is 'CLK~1'
-- Equation name is 'CLK~1', location is LC1_B21, type is buried.
-- synthesized logic cell
_LC1_B21 = LCELL( F1KHZ);
-- Node name is ':13' = 'COUT0'
-- Equation name is 'COUT0', location is LC2_B16, type is buried.
COUT0 = DFFE( _EQ001, GLOBAL( F1KHZ), VCC, VCC, VCC);
_EQ001 = !COUT0 & _LC1_B14;
-- Node name is ':12' = 'COUT1'
-- Equation name is 'COUT1', location is LC1_B16, type is buried.
COUT1 = DFFE( _EQ002, GLOBAL( F1KHZ), VCC, VCC, VCC);
_EQ002 = COUT0 & !COUT1 & _LC1_B14
# !COUT0 & COUT1 & _LC1_B14;
-- Node name is ':11' = 'COUT2'
-- Equation name is 'COUT2', location is LC3_B16, type is buried.
COUT2 = DFFE( _EQ003, GLOBAL( F1KHZ), VCC, VCC, VCC);
_EQ003 = !COUT0 & COUT2 & _LC1_B14
# !COUT1 & COUT2 & _LC1_B14
# COUT0 & COUT1 & !COUT2 & _LC1_B14;
-- Node name is ':10' = 'COUT3'
-- Equation name is 'COUT3', location is LC3_B14, type is buried.
COUT3 = DFFE( _EQ004, GLOBAL( F1KHZ), VCC, VCC, VCC);
_EQ004 = COUT3 & _LC1_B14 & !_LC4_B16
# !COUT3 & _LC1_B14 & _LC4_B16;
-- Node name is ':9' = 'COUT4'
-- Equation name is 'COUT4', location is LC2_B14, type is buried.
COUT4 = DFFE( _EQ005, GLOBAL( F1KHZ), VCC, VCC, VCC);
_EQ005 = !COUT3 & COUT4 & _LC1_B14
# COUT4 & _LC1_B14 & !_LC4_B16
# COUT3 & !COUT4 & _LC1_B14 & _LC4_B16;
-- Node name is ':8' = 'COUT5'
-- Equation name is 'COUT5', location is LC6_B13, type is buried.
COUT5 = DFFE( _EQ006, GLOBAL( F1KHZ), VCC, VCC, VCC);
_EQ006 = !COUT4 & COUT5 & _LC1_B14
# COUT5 & _LC1_B14 & !_LC8_B14
# COUT4 & !COUT5 & _LC1_B14 & _LC8_B14;
-- Node name is ':7' = 'COUT6'
-- Equation name is 'COUT6', location is LC8_B13, type is buried.
COUT6 = DFFE( _EQ007, GLOBAL( F1KHZ), VCC, VCC, VCC);
_EQ007 = COUT6 & _LC1_B14 & !_LC3_B13
# !COUT6 & _LC1_B14 & _LC3_B13;
-- Node name is ':6' = 'COUT7'
-- Equation name is 'COUT7', location is LC7_B13, type is buried.
COUT7 = DFFE( _EQ008, GLOBAL( F1KHZ), VCC, VCC, VCC);
_EQ008 = !COUT6 & COUT7 & _LC1_B14
# COUT7 & _LC1_B14 & !_LC3_B13
# COUT6 & !COUT7 & _LC1_B14 & _LC3_B13;
-- Node name is ':5' = 'COUT8'
-- Equation name is 'COUT8', location is LC5_B13, type is buried.
COUT8 = DFFE( _EQ009, GLOBAL( F1KHZ), VCC, VCC, VCC);
_EQ009 = COUT8 & _LC1_B14 & !_LC4_B13
# !COUT8 & _LC1_B14 & _LC4_B13;
-- Node name is ':4' = 'COUT9'
-- Equation name is 'COUT9', location is LC2_B13, type is buried.
COUT9 = DFFE( _EQ010, GLOBAL( F1KHZ), VCC, VCC, VCC);
_EQ010 = !COUT8 & COUT9 & _LC1_B14
# COUT9 & _LC1_B14 & !_LC4_B13
# COUT8 & !COUT9 & _LC1_B14 & _LC4_B13;
-- Node name is 'F1HZ'
-- Equation name is 'F1HZ', type is output
F1HZ = _LC8_B16;
-- Node name is '|LPM_ADD_SUB:161|addcore:adder|:87' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC4_B16', type is buried
_LC4_B16 = LCELL( _EQ011);
_EQ011 = COUT0 & COUT1 & COUT2;
-- Node name is '|LPM_ADD_SUB:161|addcore:adder|:91' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC8_B14', type is buried
_LC8_B14 = LCELL( _EQ012);
_EQ012 = COUT3 & _LC4_B16;
-- Node name is '|LPM_ADD_SUB:161|addcore:adder|:99' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC3_B13', type is buried
_LC3_B13 = LCELL( _EQ013);
_EQ013 = COUT3 & COUT4 & COUT5 & _LC4_B16;
-- Node name is '|LPM_ADD_SUB:161|addcore:adder|:107' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC4_B13', type is buried
_LC4_B13 = LCELL( _EQ014);
_EQ014 = COUT6 & COUT7 & _LC3_B13;
-- Node name is ':73'
-- Equation name is '_LC1_B14', type is buried
_LC1_B14 = LCELL( _EQ015);
_EQ015 = _LC4_B14 & !_LC4_B16
# !COUT9
# !_LC1_B13;
-- Node name is '~95~1'
-- Equation name is '~95~1', location is LC4_B14, type is buried.
-- synthesized logic cell
_LC4_B14 = LCELL( _EQ016);
_EQ016 = !COUT3 & !COUT4;
-- Node name is '~491~1'
-- Equation name is '~491~1', location is LC1_B13, type is buried.
-- synthesized logic cell
!_LC1_B13 = _LC1_B13~NOT;
_LC1_B13~NOT = LCELL( _EQ017);
_EQ017 = !COUT8
# !COUT5
# !COUT7
# !COUT6;
-- Node name is '~491~2'
-- Equation name is '~491~2', location is LC6_B16, type is buried.
-- synthesized logic cell
_LC6_B16 = LCELL( _EQ018);
_EQ018 = !COUT2 & !COUT3 & COUT4 & !COUT9;
-- Node name is ':491'
-- Equation name is '_LC7_B16', type is buried
_LC7_B16 = LCELL( _EQ019);
_EQ019 = COUT0 & COUT1 & _LC1_B13 & _LC6_B16;
-- Node name is ':494'
-- Equation name is '_LC8_B16', type is buried
_LC8_B16 = LCELL( _EQ020);
_EQ020 = _LC5_B16 & _LC8_B16
# !COUT2 & _LC8_B16
# _LC7_B16;
-- Node name is '~496~1'
-- Equation name is '~496~1', location is LC5_B16, type is buried.
-- synthesized logic cell
_LC5_B16 = LCELL( _EQ021);
_EQ021 = COUT4
# COUT3
# !COUT9
# !_LC1_B13;
Project Information g:\eda\max_pl~1\besteve\quzheng\fenpinqi.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Multi-Level
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'FLEX10K' family
CARRY_CHAIN = ignore
CARRY_CHAIN_LENGTH = 32
CASCADE_CHAIN = ignore
CASCADE_CHAIN_LENGTH = 2
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SUBFACTOR_EXTRACTION = on
IGNORE_SOFT_BUFFERS = on
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Use Quartus Fitter = on
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:00
Database Builder 00:00:00
Logic Synthesizer 00:00:00
Partitioner 00:00:00
Fitter 00:00:02
Timing SNF Extractor 00:00:00
Assembler 00:00:00
-------------------------- --------
Total Time 00:00:02
Memory Allocated
-----------------
Peak memory allocated during compilation = 12,966K
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