📄 jpq.rpt
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Total single-pin Output Enables required: 0
Synthesized logic cells: 18/ 576 ( 3%)
Logic Cell and Embedded Cell Counts
Column: 01 02 03 04 05 06 07 08 09 10 11 12 EA 13 14 15 16 17 18 19 20 21 22 23 24 Total(LC/EC)
A: 0 8 8 8 0 1 8 0 1 8 8 8 0 0 0 0 0 0 0 0 0 0 0 0 0 58/0
B: 0 0 0 0 1 0 8 8 8 1 0 8 0 8 8 8 8 1 1 8 8 1 8 8 8 109/0
C: 0 8 8 0 0 0 0 0 7 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 23/0
Total: 0 16 16 8 1 1 16 8 16 9 8 16 0 8 8 8 8 1 1 8 8 1 8 8 8 190/0
Device-Specific Information: h:\eda\max+plus ii\besteve\test\jpq.rpt
jpq
** INPUTS **
Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
1 - - - -- INPUT G 0 0 0 0 FIN
43 - - - -- INPUT G 0 0 0 0 F1KHZ
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
G = Global Source. Fan-out destinations counted here do not include destinations
that are driven using global routing resources. Refer to the Auto Global Signals,
Clock Signals, Clear Signals, Synchronous Load Signals, and Synchronous Clear Signals
Sections of this Report File for information on which signals' fan-outs are used as
Clock, Clear, Preset, Output Enable, and synchronous Load signals.
Device-Specific Information: h:\eda\max+plus ii\besteve\test\jpq.rpt
jpq
** OUTPUTS **
Fed By Fed By Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
21 - - B -- OUTPUT 0 1 0 0 COUTT
67 - - B -- OUTPUT 0 1 0 0 DISBLAY0
22 - - B -- OUTPUT 0 1 0 0 DISBLAY1
23 - - B -- OUTPUT 0 1 0 0 DISBLAY2
65 - - B -- OUTPUT 0 1 0 0 DISBLAY3
25 - - B -- OUTPUT 0 1 0 0 DISBLAY4
66 - - B -- OUTPUT 0 1 0 0 DISBLAY5
24 - - B -- OUTPUT 0 1 0 0 DISBLAY6
16 - - A -- OUTPUT 0 1 0 0 KEY0
18 - - A -- OUTPUT 0 1 0 0 KEY1
17 - - A -- OUTPUT 0 1 0 0 KEY2
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
Device-Specific Information: h:\eda\max+plus ii\besteve\test\jpq.rpt
jpq
** BURIED LOGIC **
Fan-In Fan-Out
IOC LC EC Row Col Primitive Code INP FBK OUT FBK Name
- 8 - A 04 AND2 0 2 0 1 |CNT10:13|LPM_ADD_SUB:52|addcore:adder|:55
- 6 - A 04 OR2 0 4 0 1 |CNT10:13|LPM_ADD_SUB:52|addcore:adder|:69
- 1 - A 04 DFFE + 0 4 0 4 |CNT10:13|CQI3 (|CNT10:13|:11)
- 3 - A 04 DFFE + 0 4 0 4 |CNT10:13|CQI2 (|CNT10:13|:12)
- 5 - A 04 DFFE + 0 4 0 5 |CNT10:13|CQI1 (|CNT10:13|:13)
- 4 - A 04 DFFE + 0 3 0 6 |CNT10:13|CQI0 (|CNT10:13|:14)
- 7 - A 04 OR2 0 4 0 4 |CNT10:13|:31
- 2 - A 04 AND2 0 4 0 4 |CNT10:13|:117
- 8 - A 02 AND2 0 2 0 1 |CNT10:14|LPM_ADD_SUB:52|addcore:adder|:55
- 6 - A 02 OR2 0 4 0 1 |CNT10:14|LPM_ADD_SUB:52|addcore:adder|:69
- 5 - A 02 DFFE 0 5 0 4 |CNT10:14|CQI3 (|CNT10:14|:11)
- 4 - A 02 DFFE 0 5 0 4 |CNT10:14|CQI2 (|CNT10:14|:12)
- 3 - A 02 DFFE 0 5 0 5 |CNT10:14|CQI1 (|CNT10:14|:13)
- 2 - A 02 DFFE 0 4 0 6 |CNT10:14|CQI0 (|CNT10:14|:14)
- 7 - A 02 OR2 0 4 0 4 |CNT10:14|:31
- 1 - A 02 AND2 0 4 0 4 |CNT10:14|:117
- 3 - A 11 AND2 0 2 0 1 |CNT10:15|LPM_ADD_SUB:52|addcore:adder|:55
- 8 - A 11 OR2 0 4 0 1 |CNT10:15|LPM_ADD_SUB:52|addcore:adder|:69
- 2 - A 11 DFFE 0 5 0 4 |CNT10:15|CQI3 (|CNT10:15|:11)
- 4 - A 11 DFFE 0 5 0 4 |CNT10:15|CQI2 (|CNT10:15|:12)
- 1 - A 11 DFFE 0 5 0 5 |CNT10:15|CQI1 (|CNT10:15|:13)
- 5 - A 11 DFFE 0 4 0 6 |CNT10:15|CQI0 (|CNT10:15|:14)
- 6 - A 11 OR2 0 4 0 4 |CNT10:15|:31
- 7 - A 11 AND2 0 4 0 4 |CNT10:15|:117
- 7 - B 24 AND2 0 2 0 1 |CNT10:16|LPM_ADD_SUB:52|addcore:adder|:55
- 8 - B 24 OR2 0 4 0 1 |CNT10:16|LPM_ADD_SUB:52|addcore:adder|:69
- 5 - B 24 DFFE 0 5 0 4 |CNT10:16|CQI3 (|CNT10:16|:11)
- 4 - B 24 DFFE 0 5 0 4 |CNT10:16|CQI2 (|CNT10:16|:12)
- 1 - B 24 DFFE 0 5 0 5 |CNT10:16|CQI1 (|CNT10:16|:13)
- 3 - B 24 DFFE 0 4 0 6 |CNT10:16|CQI0 (|CNT10:16|:14)
- 6 - B 24 OR2 0 4 0 4 |CNT10:16|:31
- 2 - B 24 AND2 0 4 0 4 |CNT10:16|:117
- 7 - B 19 AND2 0 2 0 1 |CNT10:17|LPM_ADD_SUB:52|addcore:adder|:55
- 8 - B 19 OR2 0 4 0 1 |CNT10:17|LPM_ADD_SUB:52|addcore:adder|:69
- 2 - B 19 DFFE 0 5 0 4 |CNT10:17|CQI3 (|CNT10:17|:11)
- 4 - B 19 DFFE 0 5 0 4 |CNT10:17|CQI2 (|CNT10:17|:12)
- 3 - B 19 DFFE 0 5 0 5 |CNT10:17|CQI1 (|CNT10:17|:13)
- 1 - B 19 DFFE 0 4 0 6 |CNT10:17|CQI0 (|CNT10:17|:14)
- 6 - B 19 OR2 0 4 0 4 |CNT10:17|:31
- 5 - B 19 AND2 0 4 0 4 |CNT10:17|:117
- 7 - B 23 AND2 0 2 0 1 |CNT10:18|LPM_ADD_SUB:52|addcore:adder|:55
- 8 - B 23 OR2 0 4 0 1 |CNT10:18|LPM_ADD_SUB:52|addcore:adder|:69
- 2 - B 23 DFFE 0 5 0 4 |CNT10:18|CQI3 (|CNT10:18|:11)
- 3 - B 23 DFFE 0 5 0 4 |CNT10:18|CQI2 (|CNT10:18|:12)
- 4 - B 23 DFFE 0 5 0 5 |CNT10:18|CQI1 (|CNT10:18|:13)
- 1 - B 23 DFFE 0 4 0 6 |CNT10:18|CQI0 (|CNT10:18|:14)
- 6 - B 23 OR2 0 4 0 4 |CNT10:18|:31
- 5 - B 23 AND2 0 4 0 4 |CNT10:18|:117
- 7 - B 14 AND2 0 2 0 1 |CNT10:19|LPM_ADD_SUB:52|addcore:adder|:55
- 8 - B 14 OR2 0 4 0 1 |CNT10:19|LPM_ADD_SUB:52|addcore:adder|:69
- 2 - B 14 DFFE 0 5 0 4 |CNT10:19|CQI3 (|CNT10:19|:11)
- 3 - B 14 DFFE 0 5 0 4 |CNT10:19|CQI2 (|CNT10:19|:12)
- 4 - B 14 DFFE 0 5 0 5 |CNT10:19|CQI1 (|CNT10:19|:13)
- 1 - B 14 DFFE 0 4 0 6 |CNT10:19|CQI0 (|CNT10:19|:14)
- 6 - B 14 OR2 0 4 0 4 |CNT10:19|:31
- 5 - B 14 AND2 0 4 0 4 |CNT10:19|:117
- 5 - B 16 AND2 0 2 0 1 |CNT10:20|LPM_ADD_SUB:52|addcore:adder|:55
- 7 - B 16 OR2 0 4 0 1 |CNT10:20|LPM_ADD_SUB:52|addcore:adder|:69
- 6 - B 16 DFFE 0 5 0 4 |CNT10:20|CQI3 (|CNT10:20|:11)
- 3 - B 16 DFFE 0 5 0 4 |CNT10:20|CQI2 (|CNT10:20|:12)
- 2 - B 16 DFFE 0 5 0 5 |CNT10:20|CQI1 (|CNT10:20|:13)
- 8 - B 16 DFFE 0 4 0 6 |CNT10:20|CQI0 (|CNT10:20|:14)
- 4 - B 16 OR2 0 4 0 4 |CNT10:20|:31
- 1 - B 16 AND2 0 4 1 0 |CNT10:20|:117
- 8 - B 09 OR2 s ! 0 3 0 1 |DECL7S:1|~251~1
- 7 - B 09 AND2 s ! 0 3 0 7 |DECL7S:1|~263~1
- 5 - B 12 AND2 0 2 0 1 |DECL7S:1|:263
- 8 - B 12 OR2 0 4 0 1 |DECL7S:1|:280
- 4 - B 09 AND2 s 0 3 0 6 |DECL7S:1|~287~1
- 4 - B 07 OR2 ! 0 2 0 1 |DECL7S:1|:299
- 3 - B 12 AND2 0 2 0 1 |DECL7S:1|:311
- 6 - B 09 AND2 s 0 3 0 4 |DECL7S:1|~323~1
- 2 - B 12 OR2 ! 0 2 0 1 |DECL7S:1|:323
- 2 - B 08 OR2 s 0 3 0 4 |DECL7S:1|~326~1
- 2 - B 09 OR2 s 0 3 0 7 |DECL7S:1|~347~1
- 8 - B 07 AND2 0 2 0 1 |DECL7S:1|:347
- 6 - B 12 OR2 0 4 1 1 |DECL7S:1|:350
- 1 - B 12 AND2 s ! 0 1 0 2 |DECL7S:1|~352~1
- 5 - B 09 OR2 0 4 0 1 |DECL7S:1|:367
- 3 - B 07 OR2 0 4 1 1 |DECL7S:1|:383
- 6 - B 07 OR2 s ! 0 3 0 2 |DECL7S:1|~385~1
- 5 - B 08 OR2 0 4 0 1 |DECL7S:1|:398
- 6 - B 08 OR2 0 4 0 1 |DECL7S:1|:410
- 7 - B 08 OR2 0 3 1 1 |DECL7S:1|:416
- 3 - B 08 OR2 0 4 0 1 |DECL7S:1|:433
- 4 - B 08 OR2 0 4 0 1 |DECL7S:1|:442
- 8 - B 08 OR2 0 4 1 1 |DECL7S:1|:449
- 3 - B 09 OR2 s 0 3 0 2 |DECL7S:1|~473~1
- 1 - B 08 OR2 s 0 3 0 3 |DECL7S:1|~473~2
- 7 - B 12 OR2 s 0 4 0 1 |DECL7S:1|~473~3
- 4 - B 12 OR2 0 3 1 0 |DECL7S:1|:482
- 1 - B 09 AND2 s 0 3 0 5 |DECL7S:1|~494~1
- 7 - B 07 OR2 s 0 4 0 1 |DECL7S:1|~515~1
- 2 - B 07 OR2 0 3 1 0 |DECL7S:1|:515
- 5 - B 07 OR2 0 4 0 1 |DECL7S:1|:541
- 1 - B 05 AND2 s 0 1 0 4 |DECL7S:1|~542~1
- 1 - B 07 OR2 0 4 1 1 |DECL7S:1|:548
- 2 - A 12 DFFE + 0 3 1 7 |DISPLAY:60|COUTI2 (|DISPLAY:60|:42)
- 5 - A 03 DFFE + 0 2 1 8 |DISPLAY:60|COUTI1 (|DISPLAY:60|:43)
- 1 - A 03 DFFE + 0 1 1 9 |DISPLAY:60|COUTI0 (|DISPLAY:60|:44)
- 5 - A 12 AND2 0 3 0 4 |DISPLAY:60|:357
- 5 - B 20 OR2 ! 0 3 0 1 |DISPLAY:60|:360
- 8 - A 12 OR2 ! 0 3 0 4 |DISPLAY:60|:367
- 7 - B 20 OR2 ! 0 3 0 1 |DISPLAY:60|:370
- 7 - A 12 AND2 0 3 0 5 |DISPLAY:60|:377
- 8 - B 20 OR2 ! 0 3 0 1 |DISPLAY:60|:380
- 6 - A 12 AND2 0 3 0 4 |DISPLAY:60|:387
- 1 - B 20 OR2 ! 0 3 0 1 |DISPLAY:60|:390
- 4 - A 12 AND2 0 3 0 4 |DISPLAY:60|:397
- 7 - A 07 OR2 ! 0 3 0 1 |DISPLAY:60|:400
- 3 - A 12 AND2 0 3 0 5 |DISPLAY:60|:407
- 8 - A 07 OR2 ! 0 3 0 1 |DISPLAY:60|:410
- 1 - A 12 AND2 0 3 0 4 |DISPLAY:60|:417
- 4 - A 07 OR2 ! 0 3 0 6 |DISPLAY:60|:420
- 5 - B 13 OR2 0 3 0 1 |DISPLAY:60|:426
- 6 - B 13 OR2 0 3 0 1 |DISPLAY:60|:429
- 8 - B 13 OR2 0 3 0 1 |DISPLAY:60|:432
- 1 - B 13 OR2 0 3 0 1 |DISPLAY:60|:435
- 4 - A 03 OR2 0 3 0 1 |DISPLAY:60|:438
- 7 - A 03 OR2 0 3 0 1 |DISPLAY:60|:441
- 2 - A 03 OR2 0 3 0 6 |DISPLAY:60|:444
- 5 - B 15 OR2 0 3 0 1 |DISPLAY:60|:450
- 6 - B 15 OR2 0 3 0 1 |DISPLAY:60|:453
- 8 - B 15 OR2 0 3 0 1 |DISPLAY:60|:456
- 2 - B 15 OR2 0 3 0 1 |DISPLAY:60|:459
- 5 - A 10 OR2 0 3 0 1 |DISPLAY:60|:462
- 7 - A 10 OR2 0 3 0 1 |DISPLAY:60|:465
- 1 - A 10 OR2 0 3 0 6 |DISPLAY:60|:468
- 4 - B 22 OR2 0 3 0 1 |DISPLAY:60|:474
- 7 - B 22 AND2 0 2 0 1 |DISPLAY:60|:481
- 5 - B 22 OR2 0 4 0 1 |DISPLAY:60|:482
- 1 - B 22 OR2 0 4 0 1 |DISPLAY:60|:483
- 2 - A 10 AND2 0 2 0 1 |DISPLAY:60|:490
- 3 - A 07 OR2 0 4 0 1 |DISPLAY:60|:491
- 1 - A 07 OR2 0 4 0 19 |DISPLAY:60|:492
- 4 - C 03 AND2 0 3 0 5 |FENPINQI:54|LPM_ADD_SUB:161|addcore:adder|:87
- 6 - C 09 AND2 0 2 0 1 |FENPINQI:54|LPM_ADD_SUB:161|addcore:adder|:91
- 1 - C 02 AND2 0 4 0 3 |FENPINQI:54|LPM_ADD_SUB:161|addcore:adder|:99
- 2 - C 02 AND2 0 3 0 2 |FENPINQI:54|LPM_ADD_SUB:161|addcore:adder|:107
- 8 - C 02 DFFE + 0 3 0 3 |FENPINQI:54|COUT9 (|FENPINQI:54|:4)
- 3 - C 02 DFFE + 0 2 0 2 |FENPINQI:54|COUT8 (|FENPINQI:54|:5)
- 6 - C 02 DFFE + 0 3 0 2 |FENPINQI:54|COUT7 (|FENPINQI:54|:6)
- 7 - C 02 DFFE + 0 2 0 3 |FENPINQI:54|COUT6 (|FENPINQI:54|:7)
- 5 - C 02 DFFE + 0 3 0 2 |FENPINQI:54|COUT5 (|FENPINQI:54|:8)
- 5 - C 09 DFFE + 0 3 0 5 |FENPINQI:54|COUT4 (|FENPINQI:54|:9)
- 8 - C 09 DFFE + 0 2 0 6 |FENPINQI:54|COUT3 (|FENPINQI:54|:10)
- 5 - C 03 DFFE + 0 3 0 3 |FENPINQI:54|COUT2 (|FENPINQI:54|:11)
- 2 - C 03 DFFE + 0 2 0 3 |FENPINQI:54|COUT1 (|FENPINQI:54|:12)
- 3 - C 03 DFFE + 0 1 0 4 |FENPINQI:54|COUT0 (|FENPINQI:54|:13)
- 4 - C 09 OR2 0 4 0 10 |FENPINQI:54|:73
- 2 - C 09 AND2 s 0 2 0 1 |FENPINQI:54|~95~1
- 4 - C 02 OR2 s ! 0 4 0 3 |FENPINQI:54|~491~1
- 7 - C 03 AND2 s 0 4 0 1 |FENPINQI:54|~491~2
- 8 - C 03 AND2 0 4 0 1 |FENPINQI:54|:491
- 1 - C 03 OR2 0 3 0 2 |FENPINQI:54|:494
- 6 - C 03 OR2 s 0 4 0 1 |FENPINQI:54|~496~1
- 2 - A 06 DFFE 0 2 0 1 |REG4B:2|:6
- 8 - A 03 DFFE 0 2 0 1 |REG4B:2|:8
- 8 - A 10 DFFE 0 2 0 1 |REG4B:2|:10
- 5 - A 07 DFFE 0 2 0 1 |REG4B:2|:12
- 6 - A 07 DFFE 0 2 0 1 |REG4B:21|:6
- 6 - A 03 DFFE 0 2 0 1 |REG4B:21|:8
- 6 - A 10 DFFE 0 2 0 1 |REG4B:21|:10
- 3 - A 10 DFFE 0 2 0 1 |REG4B:21|:12
- 2 - A 09 DFFE 0 2 0 1 |REG4B:22|:6
- 3 - A 03 DFFE 0 2 0 1 |REG4B:22|:8
- 4 - A 10 DFFE 0 2 0 1 |REG4B:22|:10
- 2 - A 07 DFFE 0 2 0 1 |REG4B:22|:12
- 2 - B 20 DFFE 0 2 0 1 |REG4B:23|:6
- 1 - B 18 DFFE 0 2 0 1 |REG4B:23|:8
- 5 - B 10 DFFE 0 2 0 1 |REG4B:23|:10
- 8 - B 22 DFFE 0 2 0 1 |REG4B:23|:12
- 3 - B 20 DFFE 0 2 0 1 |REG4B:24|:6
- 7 - B 13 DFFE 0 2 0 1 |REG4B:24|:8
- 7 - B 15 DFFE 0 2 0 1 |REG4B:24|:10
- 6 - B 22 DFFE 0 2 0 1 |REG4B:24|:12
- 6 - B 20 DFFE 0 2 0 1 |REG4B:25|:6
- 2 - B 13 DFFE 0 2 0 1 |REG4B:25|:8
- 1 - B 15 DFFE 0 2 0 1 |REG4B:25|:10
- 2 - B 22 DFFE 0 2 0 1 |REG4B:25|:12
- 1 - B 21 DFFE 0 2 0 1 |REG4B:26|:6
- 4 - B 13 DFFE 0 2 0 1 |REG4B:26|:8
- 4 - B 15 DFFE 0 2 0 1 |REG4B:26|:10
- 1 - B 17 DFFE 0 2 0 1 |REG4B:26|:12
- 4 - B 20 DFFE 0 2 0 1 |REG4B:27|:6
- 3 - B 13 DFFE 0 2 0 1 |REG4B:27|:8
- 3 - B 15 DFFE 0 2 0 1 |REG4B:27|:10
- 3 - B 22 DFFE 0 2 0 1 |REG4B:27|:12
- 1 - C 09 DFFE 0 1 0 68 |TEST:3|DIV2CLK (|TEST:3|:5)
- 7 - C 09 OR2 ! 0 2 0 32 |TEST:3|:36
Code:
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