fenpinqi.vhd

来自「测频器」· VHDL 代码 · 共 38 行

--Author    	: 屈峥 2002081212
--File Name 	: FENPINQI.vhd
--Objective 	: 分频器
--
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY FENPINQI IS
   PORT ( F1KHZ : IN STD_LOGIC;
          CLK : OUT STD_LOGIC;
          F1HZ : OUT STD_LOGIC);
 END;
ARCHITECTURE BEHAV OF FENPINQI IS
   SIGNAL COUT : INTEGER RANGE 999 DOWNTO 0;
   SIGNAL Q : STD_LOGIC;
   BEGIN
      PROCESS ( F1KHZ )
         BEGIN
         IF F1KHZ'EVENT AND F1KHZ = '1' THEN
            IF COUT < 999 THEN COUT <= COUT + 1;
             ELSE COUT <= 0;
             END IF;
          END IF;
         CASE COUT IS
            WHEN 499 => Q <= '1';
            WHEN 996 => Q <= '0';
            WHEN 997 => Q <= '0';
            WHEN 998 => Q <= '0';
            WHEN 999 => Q <= '0';
         WHEN OTHERS => NULL;
         END CASE;
         F1HZ <= Q;
         CLK <= F1KHZ;
       END PROCESS;
 END;