已通过仿真的程序.txt

此文件里为我多年收集的子程序模块源代码

library IEEE;--74LS138译码器
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity decoder3_8 is
    Port (a2,a1,a0:in std_logic;
	       g1,g2a,g2b:in std_logic;
			 y:out std_logic_vector(7 downto 0)
			 );
end decoder3_8;

architecture Behavioral of decoder3_8 is

begin
process(a0,a1,a2,g1,g2a,g2b)
variable temp:std_logic_vector(2 downto 0);
begin
temp:=a2&a1&a0;
if (g1='1' and g2a='0' and g2b='0') then
  case temp is 
    when "000"=>y<="11111110";
    when "001"=>y<="11111101";
    when "010"=>y<="11111011";
    when "011"=>y<="11110111";
    when "100"=>y<="11101111";
    when "101"=>y<="11011111";
    when "110"=>y<="10111111";
    when "111"=>y<="01111111";
    when others=>y<="--------";
  end case;
else 
  y<="11111111";
end if;
end process;
end Behavioral;

library IEEE;--半加器
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity halfadder is
    Port (a,b:in std_logic;
	       sum,count:out std_logic
			 );
end halfadder;

architecture Behavioral of halfadder is

begin
process(a,b)
begin
  if (a='1' and b='1') then count<='1';
  else count<='0';
  end if;
  if (a/=b) then sum<='1';--(a/=b) a不等于b
  else sum<='0';
  end if;
end process;
end Behavioral;

library IEEE;--半加器（利用变量）
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity halfadder1 is
    Port (a,b:in std_logic;
	  cout,sum:out std_logic
			 );
end halfadder1;

architecture Behavioral of halfadder1 is
begin
process(a,b)
variable y:std_logic_vector(1 downto 0);
begin
if (a='0' and b='0') then y:="00"; 
  elsif (a='0' and b='1') then y:="01";
  elsif (a='1' and b='0') then y:="01";
  elsif (a='1' and b='1') then y:="10";
  else y:="--";
end if;
cout<=y(1);
sum<=y(0);
end process;
end Behavioral;

library IEEE;--半加器
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity hong1 is
    Port (a,b:IN STD_LOGIC;
	 co,so:OUT STD_LOGIC);
end hong1;

architecture Behavioral of hong1 is

begin
so<=NOT(a XOR (NOT b));
co<=a AND b;

end Behavioral;

library IEEE;--半加器（注意基本语句格式）
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

--  Uncomment the following lines to use the declarations that are
--  provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;

entity half_adder is
    Port (a,b:in std_logic;
          cout,sum:out std_logic
		 );
end half_adder;

architecture Behavioral of half_adder is

begin
process(a,b)
begin
  if (a='1' and b='1') then sum<='0';cout<='1';
     else if (a='0' and b='0') then sum<='0';cout<='0';
	  else sum<='1';cout<='0';
     end if;
  end if;
end process;
end Behavioral;  

library IEEE;--半加器（此程序较灵活，注意体会！！！）
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

--  Uncomment the following lines to use the declarations that are
--  provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;

entity half_adder is
    Port (a,b:in std_logic;
          cout,sum:out std_logic
		 );
end half_adder;

architecture Behavioral of half_adder is

begin
process(a,b)
begin
  if (a='1' and b='1') then cout<='1';
    else cout<='0';
  end if;
  if (a/=b) then sum<='1';
    else sum<='0';
  end if;    
end process;
end Behavioral;  

--编写半加器，还可通过半加器的组成逻辑编VHDL源程序，即根据半加器由一个异或门与一个与门构成进行编--程  
  


library IEEE;--全加器
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity fulladd1 is
    Port (a,b,cin:in std_logic;
	       sum,cout:out std_logic
			 );
end fulladd1;

architecture Behavioral of fulladd1 is

begin
process(a,b,cin)
variable temp:std_logic_vector(2 downto 0);
begin
  temp:=a&b&cin;
  case temp is
    when "000"=>sum<='0';cout<='0';
	 when "001"=>sum<='1';cout<='0';
	 when "010"=>sum<='1';cout<='0';
	 when "011"=>sum<='0';cout<='1';
	 when "100"=>sum<='1';cout<='0';
	 when "101"=>sum<='0';cout<='1';
	 when "110"=>sum<='0';cout<='1';
	 when "111"=>sum<='1';cout<='1';
	 when others=>sum<='-';cout<='-';
end case;
end process;
end Behavioral;

library IEEE;--全加器。注意与上例对比
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity fulladd1 is
    Port (a,b,cin:in std_logic;
	       sum,cout:out std_logic
			 );
end fulladd1;

architecture Behavioral of fulladd1 is

begin
process(a,b,cin)
variable temp:std_logic_vector(2 downto 0);
begin
  temp:=a&b&cin;
  case temp is
    when "000"=>sum<='0';
	             cout<='0';
	 when "001"|"010"|"100"=>sum<='1';
	                         cout<='0';
	 when "011"|"101"|"110"=>sum<='0';
	                         cout<='1';
	 when "111"=>sum<='1';
	             cout<='1';
	 when others=>sum<='-';
	             cout<='-';
end case;
end process;
end Behavioral;


library IEEE;--优先级8-3编码器
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity precedence_code8_3 is
    Port (d:in std_logic_vector(7 downto 0);
	       y0,y1,y2:out std_logic
			 );
end precedence_code8_3;

architecture Behavioral of precedence_code8_3 is

begin
process(d)
variable temp:std_logic_vector(2 downto 0);
begin
  temp:="000";
  if (d="1000000") then temp:="111";
    elsif (d="01000000") then temp:="110";
	 elsif (d="00100000") then temp:="101";
	 elsif (d="00010000") then temp:="100";
	 elsif (d="00001000") then temp:="011";
	 elsif (d="00000100") then temp:="010";
	 elsif (d="00000010") then temp:="001";
	 elsif (d="00000001") then temp:="000";
	 else temp:="000";--注意要加此句，相当于加初始值
 end if;
   y2<=temp(2);
	y1<=temp(1);
	y0<=temp(0);
 end process;
end Behavioral;

library IEEE;--同上优先级8-3编码器
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity pre_code8_3 is
    Port (d:in std_logic_vector(7 downto 0);
	       y0,y1,y2:out std_logic
			 );
end pre_code8_3;

architecture Behavioral of pre_code8_3 is

begin
process (d)
variable temp:std_logic_vector(2 downto 0);
begin
  temp:="000";--注意该例与上例的区别，在此先赋初值
  if (d(0)='1') then
    temp:="000";
  end if;
  if (d(1)='1') then
    temp:="001";
  end if;
  if (d(2)='1') then
    temp:="010";
  end if;
  if (d(3)='1') then
    temp:="011";
  end if;
  if (d(4)='1') then
    temp:="100";
  end if;
  if (d(5)='1') then
    temp:="101";
  end if;
  if (d(6)='1') then
    temp:="110";
  end if;
  if (d(7)='1') then
    temp:="111";
  end if;
  y2<=temp(2);--注意该语句后的3条语句
  y1<=temp(1);
  y0<=temp(0);
end process;
end Behavioral;

library IEEE;--同上优先级8-3编码器
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity precedence_code8_3 is
    Port (d:in std_logic_vector(7 downto 0);
	       y0,y1,y2:out std_logic
			 );
end precedence_code8_3;

architecture Behavioral of precedence_code8_3 is

begin
process(d)
variable temp:std_logic_vector(2 downto 0);
begin
  if (d(7)='1') then temp:="111";--注此例为整体赋值
    elsif (d(6)='1') then temp:="110";
	 elsif (d(5)='1') then temp:="101";
	 elsif (d(4)='1') then temp:="100";
	 elsif (d(3)='1') then temp:="011";
	 elsif (d(2)='1') then temp:="010";
	 elsif (d(1)='1') then temp:="001";
	 elsif (d(0)='1') then temp:="000";
	 else temp:="000";
 end if;
   y2<=temp(2);
	y1<=temp(1);
	y0<=temp(0);
 end process;
end Behavioral;

library IEEE;--上同优先级8-3编码器
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity precedence_code8_3 is
    Port (d:in std_logic_vector(7 downto 0);
	       y0,y1,y2:out std_logic
			 );
end precedence_code8_3;

architecture Behavioral of precedence_code8_3 is

begin
process(d)
variable temp:std_logic_vector(2 downto 0);
begin
  if (d(7)='1') then y2<='1';y1<='1';y0<='1';--注此例为单个赋值
    elsif (d(6)='1') then y2<='1';y1<='1';y0<='0';
	 elsif (d(5)='1') then y2<='1';y1<='0';y0<='1';
	 elsif (d(4)='1') then y2<='1';y1<='0';y0<='0';
	 elsif (d(3)='1') then y2<='0';y1<='1';y0<='1';
	 elsif (d(2)='1') then y2<='0';y1<='1';y0<='0';
	 elsif (d(1)='1') then y2<='0';y1<='0';y0<='1';
	 elsif (d(0)='0') then y2<='0';y1<='0';y0<='0';
	 else y2<='0';y1<='0';y0<='0';
 end if;
end process;
end Behavioral;



触发器程序
library IEEE;--D触发器
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

--  Uncomment the following lines to use the declarations that are
--  provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;

entity a8_6 is
    Port (data,clk:in std_logic;
          q:out std_logic
		 );
end a8_6;

architecture Behavioral of a8_6 is

begin
process
begin
  wait until clk'event and clk='1';
  q<=data;
end process;
end Behavioral;

library IEEE;--带异步复位上升沿的D触发器
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

--  Uncomment the following lines to use the declarations that are
--  provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;

entity a8_6 is
    Port (data,clk,reset:in std_logic;
          q:out std_logic
		 );
end a8_6;

architecture Behavioral of a8_6 is

begin
process(reset,clk)
begin
  if reset='0' then q<='0';
    elsif clk'event and clk='1' then q<=data;
    --elsif q<=null;（出错！null常用于case语句）
  end if;
end process;
end Behavioral;

library IEEE;--带异步置位复位上升沿的D触发器
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

--  Uncomment the following lines to use the declarations that are
--  provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;

entity a8_6 is
    Port (data,clk,reset,set:in std_logic;
          q:out std_logic
		 );
end a8_6;

architecture Behavioral of a8_6 is

begin
process(reset,clk,set)--非同步复位与同步复位的区别？
begin
  if set='0' then q<='0';
    elsif set='1' and reset='0' then q<='1';
    elsif clk'event and clk='1' then q<=data;
  end if;
end process;
end Behavioral;

library IEEE;--带异步置位复位上升沿的D触发器
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

--  Uncomment the following lines to use the declarations that are
--  provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;

entity a8_6 is
    Port (data,clk,rest,set:in std_logic;
          q:out std_logic
		 );
end a8_6;

architecture Behavioral of a8_6 is

begin
process(rest,clk,set)
begin
  if set='0' then q<='0'; 
    else 
      if set='1' and rest='0' then q<='1';
        else 
	     if set='1' and rest='1' then 
	       if clk'event and clk='1' then q<=data;
	       end if;
		end if;
      end if;
  end if;        
end process;
end Behavioral;

library IEEE;--带异步复位和输入使能上升沿的D触发器
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

--  Uncomment the following lines to use the declarations that are
--  provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;

entity a8_9 is
    Port (data,clk,reset,en:in std_logic;
          q:out std_logic
		 );
end a8_9;

architecture Behavioral of a8_9 is

begin
process(reset,clk,en)
begin
  if reset='0' then q<='0';
   	else 
	  if reset='1' and en='1' then
	    if clk='1' and clk'event then q<=data;
	    end if;
	  end if; 
  end if;   
end process;
end Behavioral;


library IEEE;--带有复位和时钟使能的10进制计数器
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

--  Uncomment the following lines to use the declarations that are
--  provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;

entity Dcount is
    Port (clk,rest,en:in std_logic;
          cout:out std_logic;
		cq:out std_logic_vector(3 downto 0)
		 );
end Dcount;

architecture Behavioral of Dcount is
begin
process(clk,rest,en)
variable cq1:std_logic_vector(3 downto 0);
begin
  if rest='1' then cq1:=(others=>'0');
    elsif clk'event and clk='1' then 
      if en='1' then
	    if cq1<"1001" then cq1:=cq1+1; 
           else cq1:=(others=>'0');
	    end if;
	 end if;
  end if;
  if cq1="1001" then cout<='1';
    else cout<='0';
  end if;
  cq<=cq1;
end process;
end Behavioral;
						
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

--  Uncomment the following lines to use the declarations that are
--  provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;

entity Dcount is
    Port (clk,rest,en:in std_logic;
          cout,q:out std_logic;
		c:out std_logic_vector(3 downto 0)
          );
end Dcount;

architecture Behavioral of Dcount is
signal o:std_logic;
begin
process(clk,rest,en)
variable cq1:std_logic_vector(3 downto 0);
variable cq2:std_logic_vector(2 downto 0);
begin
  if rest='1' then cq1:="0000";
    elsif clk'event and clk='1' then 
      if en='1' then
	    if cq1="1001" then cq1:="0000";cout<='1'; 
           else cq1:=cq1+1;cout<='0';
	    end if;
	 end if;
  end if;
  c<=cq1;  --十进制输出波形
end process;
process(clk,rest)
variable qn:std_logic_vector(3 downto 0);
begin  
  if rest='1' then qn:="0000"; 
    elsif clk'event and clk='1' then qn:=qn+1;
      if qn="0101" then o<='1';
	   else if qn="1010" then o<='0';qn:="0000";
             end if;
	 end if;
  end if;					
  q<=o;	--占空比50％的波形。通过设置qn的值可得不同占空比。
end process;
end Behavioral;