test_parity.v

来自「奇偶校验码的VERILOG源码」· Verilog 代码 · 共 39 行

//*************************************************************************
//                  chanllege cup 2006
//                  qidifeng@isee  2006.3.17
//*************************************************************************
//parity_test.v
`timescale 10ns/1ns

module	test;

reg	[7:0]	data_origin;
reg		ctrl_mode;

wire	[8:0]	data_encoded;
wire	[7:0]	data_decoded;

wire		error;

initial
begin
	data_origin=0;ctrl_mode=1;
#10	data_origin=8'h55;
#10	data_origin=8'h99;

#10	data_origin=8'h55;ctrl_mode=0;
#10     data_origin=8'h99;
#10	$finish;
end

parity_encode		ENCODE( .data_in(data_origin), 
                        .ctrl_mode(ctrl_mode), 
                        .data_out(data_encoded));
                        
parity_decode   DECODE(.data_in(data_encoded), 
                      .ctrl_mode(ctrl_mode), 
                     .data_out(data_decoded), 
                     .error(error));

endmodule