parity_encode.v

来自「奇偶校验码的VERILOG源码」· Verilog 代码 · 共 21 行

//*************************************************************************
//                  chanllege cup 2006
//                  qidifeng@isee  2006.3.17
//*************************************************************************
//parity_encode.v
module   parity_encode( data_in, ctrl_mode, data_out);
input [7:0]	    data_in;
input 		ctrl_mode;
output	[8:0]	data_out;

wire		parity;
                //if ctrl_mode=1,  even check
                //if ctrl_mode=0,  odd  check
assign  		parity= ctrl_mode? ^data_in[7:0]: ~^data_in[7:0];   
                
                //the highst bit of data_out[8:0] is the parity bit;
assign		data_out[8:0]={parity, data_in[7:0]};

endmodule