parity_decode.v

奇偶校验码的VERILOG源码

//*************************************************************************
//                  chanllege cup 2006
//                  qidifeng@isee  2006.3.17
//*************************************************************************
//parity_decode.v
module		parity_decode(data_in, ctrl_mode, data_out, error);
input	[8:0]	data_in;
input		ctrl_mode;
output	[7:0]	data_out;
output		error;

assign	error=ctrl_mode? ^data_in[8:0]: ~^data_in[8:0];
assign	data_out[7:0]=data_in[7:0];

endmodule