test_crc.v

CRC循环校验码的VERILOG源文件

/******************************************************************/
//MODULE :crc

/***************************************************************/
`timescale 1ns/1ns
module test_crc;
reg clk;
reg reset;
reg bit_in;

wire [7:0] data_out;

always #10 clk=~clk;

initial
begin
clk=0;
reset=1;
bit_in=0;
#10 reset=0;bit_in=1;
#10 bit_in=0;
#10 bit_in=0;
#10 bit_in=1;
#10 bit_in=1;
#10 bit_in=0;
#10 bit_in=0;
#10 bit_in=0;
#10 bit_in=1;
#10 bit_in=0;
#10 bit_in=1;
#10 bit_in=0;
#10 bit_in=0;
#10 bit_in=1;
#10 bit_in=1;
#10 bit_in=0;
#10 bit_in=1;
#10 bit_in=0;

#10 bit_in=1;
#10 bit_in=0;
#10 bit_in=1;
#10 bit_in=1;
#10 $stop;


end
CRC crc(clk,reset,bit_in,data_out);
endmodule