crc.v

CRC循环校验码的VERILOG源文件

/******************************************************************/
//MODULE :crc

/***************************************************************/
//DEFINES
`define DEL 1
`define TAPS 16'b1000_1000_0001_0000  //???????
//????
module CRC(clk,reset,bit_in,data_out);
//????
input clk;
input reset;
input bit_in;

output[7:0] data_out;
wire clk;
wire reset;
wire bit_in;
reg[7:0] data_out;

always@(posedge clk)
begin
         if(reset)
                    begin    data_out<=#`DEL 8'h0;    end
        else     
                    begin    if (data_out[7])
                                           begin data_out<=#`DEL (data_out^`TAPS)<<1;
                                                       data_out[0]<=#`DEL ~bit_in;
                                            end
                                  else
                                           begin data_out<=#`DEL data_out<<1;
                                                       data_out<=#`DEL bit_in;
                                           end
                      end
end
endmodule