frame.v

来自「帧同步模块的Veriolog源码。 在ModelSim下的一个工程。有测试文件」· Verilog 代码 · 共 90 行

//*******************************************************************************
//                         FRAME SYNC    
//              qidifeng@isee            2006.3.20
//*******************************************************************************
//frame.v

module		frame(clk, rst_n, seri_in, seri_out, frame);
input		clk;
input		rst_n;
input		seri_in;

output		seri_out;
output		frame;

reg	[6:0]	seri_snyc;
wire		bark_t;
wire		bark_f;
wire		clk_div32;

reg	[6:0]	div32_cnt;
reg		state;//not actully a reg

reg		currentState,nextState;
parameter		CAP=1'b0,
		SUS=1'b1;

//regonize the bark code  1110010
always@(posedge clk)
	if(!rst_n)		seri_snyc[6:0]<=0;
	else
			begin
			seri_snyc[6:1]<=seri_snyc[5:0];
			seri_snyc[0]<=seri_in;
			end

assign		seri_out=seri_snyc[6];
assign		bark_t=~seri_snyc[0]&seri_snyc[1]&~seri_snyc[2]&~seri_snyc[3]&seri_snyc[4]&seri_snyc[5]&seri_snyc[6];
assign		bark_f=(~seri_snyc[0]+seri_snyc[1]+~seri_snyc[2]+~seri_snyc[3]+
                        seri_snyc[4]+seri_snyc[5]+seri_snyc[6]==3'h6)?1:0;
                         

//divid the clk 32
always@(posedge clk)
	if(
	   !rst_n//system start
	   |(state==0&bark_t)//state is captrure and regonize bark right
	   |(state==1&(bark_t|bark_f)&clk_div32)//state is sustain 
	   )
	   	div32_cnt[6:0]<=0;
	  else
	  	div32_cnt[6:0]<=div32_cnt[6:0]+1;
	  	
assign	clk_div32=div32_cnt[4]&div32_cnt[3]&div32_cnt[2]&div32_cnt[1]&div32_cnt[0];
assign	sync_lost=div32_cnt[4]&div32_cnt[3]&div32_cnt[2]&div32_cnt[1]&div32_cnt[0]&div32_cnt[5]&div32_cnt[6];

//state machine
	   	
always@(*)
	case(currentState)
		CAP: begin	nextState=(bark_t==1)?SUS:CAP; state=0;  end
		SUS: begin	nextState=(sync_lost==1)?CAP:SUS; state=1; end
	endcase
always@(posedge clk)
	if(!rst_n)
		currentState<=CAP;
	else
		currentState<=nextState;
		
assign	frame=state&clk_div32;

endmodule