control.vhd

这是一个自动售货机的vhdl源码

library ieee;
use ieee.std_logic_1164.all;
package state_pack is
 type state is (qa,qb);
  end state_pack;
library ieee;
use ieee.std_logic_1164.all;
use work.state_pack.all;
entity control is
    port( start,cp,T:in std_logic;
          d,b:in integer range 0 to 9;
          en1,en2,en3:out std_logic;
          reset,out1,reject1,reject2:out std_logic;
          c:out integer range 0 to 9);
end control;
architecture con of control is
signal current_state:state:=qa;
begin 
 process
  variable var: integer range 0 to 9;
 begin
   wait until cp='1'and cp'event;
   if start='1'then
    current_state<=qa;
    c<=0;reject1<='0';reject2<='0';out1<='0';
    en1<='1';reset<='0';en2<='0';en3<='0';
   end if; 
   case current_state is 
     when qa=>
          if d=0 then 
             current_state<=qa;c<=0;reject1<='0';reject2<='0';
             out1<='0';en1<='1';
             reset<='1';en2<='0';en3<='0';
          else
             current_state<=qb;var:=d;
          end if;
     when others=>
             en1<='0';reset<='0';en2<='1';en3<='1';
             if b=0 then
              reject1<='1';reject2<='0';out1<='0';
             elsif (T='0'and b<var) then
              c<=0;reject1<='1';reject2<='0';out1<='0';reset<='0';
              en1<='0';en2<='1';en3<='1';
             elsif (T='0'and b>=var)then 
              c<=b-var;reject1<='1';reject2<='1';out1<='1';reset<='0';
              en1<='0';en2<='0';en3<='1';
             elsif(T='1'and b<var)then
              c<=b;reject1<='1';reject2<='1';out1<='0';reset<='1';
              en1<='1';en2<='0';en3<='0';
             end if;
   end case;
end process;
end con;