counter.vhd

这是一个自动售货机的vhdl源码

library ieee;
use ieee.std_logic_1164.all;
entity counter is
port(A11,A21,A51,en2,cp,reset:in std_logic;
     b:out integer range 0 to 12);
end counter;
ARCHITECTURE a of counter is
  signal current_state:integer range 0 to 1;
   begin
    process
      variable var:integer range 0 to 10;
   begin
     wait until cp='1'and cp'event;
     if reset='1' then current_state<=0;b<=0;var:=0;
     else
     case current_state is
      when 0=>
        if en2='1'then 
         if A11='1'then
          current_state<=1;b<=1;var:=1;
         elsif A21='1'then
          current_state<=1;b<=2;var:=2;
         elsif A51='1'then
          current_state<=1;b<=5;var:=5;
          end if;
          end if;
      when 1=>
        if en2='1'then
         if A11='1'then var:=var+1;b<=var;
         elsif A21='1'then var:=var+2;b<=var;
         elsif A51='1'then var:=var+5;b<=var;
        end if;
        end if;
      end case;
     end if;
    end process;
   end a;