📄 food_machine.rpt
字号:
RESERVED | 15 142 | RESERVED
RESERVED | 16 141 | RESERVED
RESERVED | 17 140 | RESERVED
RESERVED | 18 139 | RESERVED
RESERVED | 19 138 | VCCIO
GND | 20 137 | GND
VCCINT | 21 136 | RESERVED
VCCIO | 22 135 | RESERVED
GND | 23 134 | RESERVED
RESERVED | 24 133 | RESERVED
led_a1 | 25 132 | RESERVED
led_b1 | 26 131 | RESERVED
led_c1 | 27 EP1K30QC208-3 130 | VCCINT
led_d1 | 28 129 | GND
led_e1 | 29 128 | RESERVED
led_f1 | 30 127 | RESERVED
led_g1 | 31 126 | RESERVED
GND | 32 125 | RESERVED
VCCINT | 33 124 | VCCINT
VCCIO | 34 123 | GND
GND | 35 122 | RESERVED
RESERVED | 36 121 | RESERVED
RESERVED | 37 120 | RESERVED
RESERVED | 38 119 | RESERVED
A1 | 39 118 | VCCIO
A4 | 40 117 | GND
A8 | 41 116 | RESERVED
VCCIO | 42 115 | RESERVED
GND | 43 114 | RESERVED
A11 | 44 113 | RESERVED
A21 | 45 112 | RESERVED
A51 | 46 111 | RESERVED
start | 47 110 | VCCIO
VCCINT | 48 109 | GND
GND | 49 108 | ^MSEL0
#TMS | 50 107 | ^MSEL1
#TRST | 51 106 | VCCINT
^nSTATUS | 52 105 | ^nCONFIG
| 54 56 58 60 62 64 66 68 70 72 74 76 78 80 82 84 86 88 90 92 94 96 98 100 102 104 _|
\ 53 55 57 59 61 63 65 67 69 71 73 75 77 79 81 83 85 87 89 91 93 95 97 99 101 103 |
\-----------------------------------------------------------------------------------------------------------
r R R R R R G R R R R R R V R R R R R V R R R G V G G G G G R V R l l l l l V l l R R R R V R R R R R R
e E E E E E N E E E E E E C E E E E E C E E E N C N N N N N E C E e e e e e C e e E E E E C E E E E E E
s S S S S S D S S S S S S C S S S S S C S S S D C D D D D D S C S d d d d d C d d S S S S C S S S S S S
e E E E E E E E E E E E I E E E E E I E E E I E I E _ _ _ _ _ I _ _ E E E E I E E E E E E
t R R R R R R R R R R R O R R R R R N R R R N R O R a b c d e N f g R R R R O R R R R R R
1 V V V V V V V V V V V V V V V V T V V V T V V T V V V V V V V V V V
E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E
D D D D D D D D D D D D D D D D D D D D D D D D D D D D D D D
N.C. = No Connect. This pin has no internal connection to the device.
VCCINT = Dedicated power pin, which MUST be connected to VCC (2.5 volts).
VCCIO = Dedicated power pin, which MUST be connected to VCC (2.5 volts).
GND = Dedicated ground pin or unused dedicated input, which MUST be connected to GND.
RESERVED = Unused I/O pin, which MUST be left unconnected.
^ = Dedicated configuration pin.
+ = Reserved configuration pin, which is tri-stated during user mode.
* = Reserved configuration pin, which drives out in user mode.
PDn = Power Down pin.
@ = Special-purpose pin.
# = JTAG Boundary-Scan Testing/In-System Programming or Configuration Pin. The JTAG inputs TMS and TDI should be tied to VCC and TCK should be tied to GND when not in use.
& = JTAG pin used for I/O. When used as user I/O, JTAG pins must be kept stable before and during configuration. JTAG pin stability prevents accidental loading of JTAG instructions.
$ = Pin has PCI I/O option enabled. Pin is neither '5.0 V'- nor '3.3 V'-tolerant.
Device-Specific Information: d:\vhdl3\food_machine.rpt
food_machine
** RESOURCE USAGE **
Logic Column Row
Array Interconnect Interconnect Clears/ External
Block Logic Cells Driven Driven Clocks Presets Interconnect
C9 1/ 8( 12%) 1/ 8( 12%) 0/ 8( 0%) 0/2 0/2 4/22( 18%)
C11 4/ 8( 50%) 2/ 8( 25%) 1/ 8( 12%) 0/2 0/2 6/22( 27%)
C13 1/ 8( 12%) 1/ 8( 12%) 0/ 8( 0%) 0/2 0/2 3/22( 13%)
C14 8/ 8(100%) 2/ 8( 25%) 3/ 8( 37%) 0/2 0/2 4/22( 18%)
C16 1/ 8( 12%) 1/ 8( 12%) 0/ 8( 0%) 0/2 0/2 4/22( 18%)
D1 8/ 8(100%) 0/ 8( 0%) 2/ 8( 25%) 1/2 1/2 3/22( 13%)
D6 8/ 8(100%) 1/ 8( 12%) 1/ 8( 12%) 1/2 0/2 14/22( 63%)
D7 8/ 8(100%) 0/ 8( 0%) 2/ 8( 25%) 1/2 1/2 3/22( 13%)
D8 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 0/2 0/2 2/22( 9%)
D9 8/ 8(100%) 1/ 8( 12%) 1/ 8( 12%) 1/2 0/2 13/22( 59%)
D10 8/ 8(100%) 1/ 8( 12%) 2/ 8( 25%) 1/2 0/2 12/22( 54%)
D11 8/ 8(100%) 1/ 8( 12%) 3/ 8( 37%) 1/2 0/2 9/22( 40%)
D12 2/ 8( 25%) 0/ 8( 0%) 2/ 8( 25%) 1/2 2/2 3/22( 13%)
D13 8/ 8(100%) 2/ 8( 25%) 2/ 8( 25%) 1/2 0/2 7/22( 31%)
D14 8/ 8(100%) 2/ 8( 25%) 2/ 8( 25%) 1/2 0/2 7/22( 31%)
D16 8/ 8(100%) 2/ 8( 25%) 3/ 8( 37%) 1/2 0/2 14/22( 63%)
D17 8/ 8(100%) 2/ 8( 25%) 4/ 8( 50%) 1/2 0/2 9/22( 40%)
D19 8/ 8(100%) 0/ 8( 0%) 2/ 8( 25%) 0/2 0/2 6/22( 27%)
D23 8/ 8(100%) 5/ 8( 62%) 6/ 8( 75%) 1/2 1/2 4/22( 18%)
D25 8/ 8(100%) 0/ 8( 0%) 6/ 8( 75%) 1/2 1/2 8/22( 36%)
D33 6/ 8( 75%) 0/ 8( 0%) 6/ 8( 75%) 0/2 0/2 6/22( 27%)
D36 8/ 8(100%) 0/ 8( 0%) 2/ 8( 25%) 0/2 0/2 5/22( 22%)
E3 6/ 8( 75%) 2/ 8( 25%) 1/ 8( 12%) 0/2 0/2 6/22( 27%)
E5 1/ 8( 12%) 1/ 8( 12%) 0/ 8( 0%) 0/2 0/2 2/22( 9%)
E6 8/ 8(100%) 2/ 8( 25%) 2/ 8( 25%) 0/2 0/2 8/22( 36%)
E8 8/ 8(100%) 3/ 8( 37%) 2/ 8( 25%) 0/2 0/2 7/22( 31%)
E10 1/ 8( 12%) 1/ 8( 12%) 1/ 8( 12%) 0/2 0/2 3/22( 13%)
F5 8/ 8(100%) 0/ 8( 0%) 4/ 8( 50%) 1/2 0/2 8/22( 36%)
F6 8/ 8(100%) 1/ 8( 12%) 3/ 8( 37%) 1/2 0/2 10/22( 45%)
F10 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 0/2 0/2 2/22( 9%)
F11 8/ 8(100%) 1/ 8( 12%) 1/ 8( 12%) 1/2 0/2 14/22( 63%)
F12 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 0/2 0/2 2/22( 9%)
F15 8/ 8(100%) 1/ 8( 12%) 2/ 8( 25%) 1/2 0/2 9/22( 40%)
F17 8/ 8(100%) 1/ 8( 12%) 1/ 8( 12%) 1/2 0/2 10/22( 45%)
F18 8/ 8(100%) 0/ 8( 0%) 5/ 8( 62%) 0/2 0/2 9/22( 40%)
F19 2/ 8( 25%) 0/ 8( 0%) 2/ 8( 25%) 1/2 2/2 3/22( 13%)
F23 8/ 8(100%) 1/ 8( 12%) 1/ 8( 12%) 1/2 1/2 3/22( 13%)
F24 8/ 8(100%) 0/ 8( 0%) 2/ 8( 25%) 1/2 1/2 3/22( 13%)
F25 8/ 8(100%) 0/ 8( 0%) 2/ 8( 25%) 1/2 1/2 3/22( 13%)
F26 8/ 8(100%) 0/ 8( 0%) 2/ 8( 25%) 1/2 1/2 3/22( 13%)
F33 2/ 8( 25%) 0/ 8( 0%) 2/ 8( 25%) 1/2 2/2 3/22( 13%)
Embedded Column Row
Array Embedded Interconnect Interconnect Read/ External
Block Cells Driven Driven Clocks Write Interconnect
Total dedicated input pins used: 0/6 ( 0%)
Total I/O pins used: 37/141 ( 26%)
Total logic cells used: 246/1728 ( 14%)
Total embedded cells used: 0/96 ( 0%)
Total EABs used: 0/6 ( 0%)
Average fan-in: 3.29/4 ( 82%)
Total fan-in: 810/6912 ( 11%)
Total input pins required: 10
Total input I/O cell registers required: 0
Total output pins required: 27
Total output I/O cell registers required: 0
Total buried I/O cell registers required: 0
Total bidirectional pins required: 0
Total reserved pins required 0
Total logic cells required: 246
Total flipflops required: 68
Total packed registers required: 0
Total logic cells in carry chains: 0
Total number of carry chains: 0
Total logic cells in cascade chains: 0
Total number of cascade chains: 0
Total single-pin Clock Enables required: 0
Total single-pin Output Enables required: 0
Synthesized logic cells: 70/1728 ( 4%)
Logic Cell and Embedded Cell Counts
Column: 01 02 03 04 05 06 07 08 09 10 11 12 13 14 15 16 17 18 EA 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 Total(LC/EC)
A: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0/0
B: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0/0
C: 0 0 0 0 0 0 0 0 1 0 4 0 1 8 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15/0
D: 8 0 0 0 0 8 8 1 8 8 8 2 8 8 0 8 8 0 0 8 0 0 0 8 0 8 0 0 0 0 0 0 0 6 0 0 8 121/0
E: 0 0 6 0 1 8 0 8 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 24/0
F: 0 0 0 0 8 8 0 0 0 1 8 1 0 0 8 0 8 8 0 2 0 0 0 8 8 8 8 0 0 0 0 0 0 2 0 0 0 86/0
Total: 8 0 6 0 9 24 8 9 9 10 20 3 9 16 8 9 16 8 0 10 0 0 0 16 8 16 8 0 0 0 0 0 0 8 0 0 8 246/0
Device-Specific Information: d:\vhdl3\food_machine.rpt
food_machine
** INPUTS **
Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
39 - - E -- INPUT ^ 0 0 0 1 A1
40 - - E -- INPUT ^ 0 0 0 1 A4
41 - - E -- INPUT ^ 0 0 0 1 A8
44 - - F -- INPUT ^ 0 0 0 1 A11
45 - - F -- INPUT ^ 0 0 0 1 A21
46 - - F -- INPUT ^ 0 0 0 1 A51
187 - - - 20 INPUT ^ 0 0 0 61 cp
8 - - A -- INPUT ^ 0 0 0 7 cp1
53 - - - 36 INPUT ^ 0 0 0 3 reset1
47 - - F -- INPUT ^ 0 0 0 19 start
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
^ = Increased input delay
* = PCI I/O is enabled
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
Device-Specific Information: d:\vhdl3\food_machine.rpt
food_machine
** OUTPUTS **
Fed By Fed By Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
86 - - - 15 OUTPUT 0 1 0 0 led_a
25 - - D -- OUTPUT 0 1 0 0 led_a1
161 - - - 04 OUTPUT 0 1 0 0 led_a2
87 - - - 14 OUTPUT 0 1 0 0 led_b
26 - - D -- OUTPUT 0 1 0 0 led_b1
162 - - - 05 OUTPUT 0 1 0 0 led_b2
88 - - - 14 OUTPUT 0 1 0 0 led_c
27 - - D -- OUTPUT 0 1 0 0 led_c1
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