count60_show.rpt

这是一个自动售货机的vhdl源码

-- Node name is ':826' 
-- Equation name is '_LC3_A20', type is buried 
_LC3_A20 = LCELL( _EQ022);
  _EQ022 =  _LC6_A20
         #  _LC7_A20
         #  _LC3_A22
         #  _LC4_A22;

-- Node name is ':856' 
-- Equation name is '_LC2_A23', type is buried 
_LC2_A23 = LCELL( _EQ023);
  _EQ023 = !_LC6_A23
         #  inte0
         #  _LC3_A22
         #  _LC4_A22;

-- Node name is '~870~1' 
-- Equation name is '~870~1', location is LC8_A14, type is buried.
-- synthesized logic cell 
_LC8_A14 = LCELL( _EQ024);
  _EQ024 =  inte1 & !inte2 & !inte3 & !inte5
         # !inte1 & !inte2 & !inte3 &  inte5
         #  inte1 & !inte2 &  inte3 &  inte5
         # !inte1 &  inte2 &  inte3 & !inte5;

-- Node name is '~870~2' 
-- Equation name is '~870~2', location is LC1_A14, type is buried.
-- synthesized logic cell 
_LC1_A14 = LCELL( _EQ025);
  _EQ025 = !inte4 &  _LC5_A14
         #  inte4 &  _LC8_A14;

-- Node name is ':879' 
-- Equation name is '_LC4_A20', type is buried 
_LC4_A20 = LCELL( _EQ026);
  _EQ026 =  inte0 &  _LC3_A14
         # !inte0 &  _LC2_A14 & !_LC3_A14
         # !inte0 &  _LC1_A14 & !_LC3_A14;

-- Node name is ':886' 
-- Equation name is '_LC8_A20', type is buried 
_LC8_A20 = LCELL( _EQ027);
  _EQ027 = !_LC3_A22 &  _LC4_A20
         #  _LC1_A23 & !_LC3_A22
         #  _LC4_A22;

-- Node name is ':898' 
-- Equation name is '_LC7_A23', type is buried 
_LC7_A23 = LCELL( _EQ028);
  _EQ028 = !inte0 &  _LC2_A14
         # !inte0 &  _LC1_A14;

-- Node name is ':910' 
-- Equation name is '_LC8_A23', type is buried 
_LC8_A23 = LCELL( _EQ029);
  _EQ029 = !inte0 &  _LC6_A23
         # !_LC3_A14 & !_LC6_A23 &  _LC7_A23
         # !inte0 & !_LC3_A14 &  _LC7_A23;

-- Node name is ':916' 
-- Equation name is '_LC3_A23', type is buried 
_LC3_A23 = LCELL( _EQ030);
  _EQ030 = !_LC3_A22 &  _LC8_A23
         #  _LC4_A22;

-- Node name is ':934' 
-- Equation name is '_LC2_A20', type is buried 
_LC2_A20 = LCELL( _EQ031);
  _EQ031 =  _LC3_A14
         # !inte0
         # !_LC2_A14;

-- Node name is ':946' 
-- Equation name is '_LC1_A20', type is buried 
_LC1_A20 = LCELL( _EQ032);
  _EQ032 = !_LC1_A23 &  _LC2_A20 & !_LC3_A22
         #  _LC4_A22;

-- Node name is '~970~1' 
-- Equation name is '~970~1', location is LC1_A23, type is buried.
-- synthesized logic cell 
_LC1_A23 = LCELL( _LC6_A23);

-- Node name is ':978' 
-- Equation name is '_LC5_A20', type is buried 
_LC5_A20 = LCELL( _EQ033);
  _EQ033 =  _LC1_A23 & !_LC3_A22 & !_LC4_A22
         #  _LC2_A20 & !_LC3_A22 & !_LC4_A22;

-- Node name is '~1117~1' 
-- Equation name is '~1117~1', location is LC8_A19, type is buried.
-- synthesized logic cell 
_LC8_A19 = LCELL( _EQ034);
  _EQ034 =  inte1
         #  inte2
         #  inte3
         # !inte4;

-- Node name is '~1117~2' 
-- Equation name is '~1117~2', location is LC4_A14, type is buried.
-- synthesized logic cell 
_LC4_A14 = LCELL( _EQ035);
  _EQ035 =  inte4
         # !inte3;

-- Node name is ':1383' 
-- Equation name is '_LC1_A22', type is buried 
!_LC1_A22 = _LC1_A22~NOT;
_LC1_A22~NOT = LCELL( _EQ036);
  _EQ036 =  inte1 &  inte2 &  inte3
         # !inte2 & !inte3
         #  _LC4_A21;

-- Node name is ':1384' 
-- Equation name is '_LC4_A18', type is buried 
_LC4_A18 = LCELL( _EQ037);
  _EQ037 =  _LC4_A14 &  _LC8_A19
         # !inte5
         # !_LC3_A18;

-- Node name is '~1516~1' 
-- Equation name is '~1516~1', location is LC2_A19, type is buried.
-- synthesized logic cell 
_LC2_A19 = LCELL( _EQ038);
  _EQ038 = !inte1 & !inte2 &  inte3
         # !inte1 & !inte2 & !inte4
         #  inte3 &  inte4
         #  inte2 &  inte4
         #  inte2 & !inte3
         # !inte3 & !inte4;

-- Node name is '~1649~1' 
-- Equation name is '~1649~1', location is LC1_A19, type is buried.
-- synthesized logic cell 
!_LC1_A19 = _LC1_A19~NOT;
_LC1_A19~NOT = LCELL( _EQ039);
  _EQ039 =  inte4
         #  inte1 &  inte3
         #  inte2 &  inte3;

-- Node name is ':1650' 
-- Equation name is '_LC7_A18', type is buried 
_LC7_A18 = LCELL( _EQ040);
  _EQ040 =  _LC2_A19 &  _LC4_A18
         #  inte5 &  _LC4_A18
         # !inte5 &  _LC1_A19;

-- Node name is '~1668~1' 
-- Equation name is '~1668~1', location is LC8_A18, type is buried.
-- synthesized logic cell 
_LC8_A18 = LCELL( _EQ041);
  _EQ041 =  inte5 & !_LC8_A19
         #  inte5 & !_LC4_A14
         # !inte5 &  _LC1_A19;

-- Node name is ':1668' 
-- Equation name is '_LC5_A18', type is buried 
_LC5_A18 = LCELL( _EQ042);
  _EQ042 =  _LC8_A18
         # !inte5 & !_LC2_A19
         # !_LC3_A18;

-- Node name is ':1686' 
-- Equation name is '_LC4_A19', type is buried 
_LC4_A19 = LCELL( _EQ043);
  _EQ043 = !inte5 &  _LC1_A19
         # !inte5 & !_LC2_A19
         # !_LC1_A22;

-- Node name is ':1704' 
-- Equation name is '_LC6_A18', type is buried 
_LC6_A18 = LCELL( _EQ044);
  _EQ044 =  _LC2_A19 &  _LC4_A18
         #  inte5 &  _LC4_A18
         # !inte5 &  _LC1_A19;

-- Node name is ':1722' 
-- Equation name is '_LC6_A19', type is buried 
_LC6_A19 = LCELL( _EQ045);
  _EQ045 = !inte5 &  _LC1_A19
         #  _LC1_A22 &  _LC2_A19
         #  inte5 &  _LC1_A22;

-- Node name is ':1740' 
-- Equation name is '_LC1_A18', type is buried 
_LC1_A18 = LCELL( _EQ046);
  _EQ046 = !inte5 &  _LC1_A19
         #  _LC2_A19 &  _LC3_A18
         #  inte5 &  _LC3_A18;

-- Node name is '~1742~1' 
-- Equation name is '~1742~1', location is LC2_A18, type is buried.
-- synthesized logic cell 
!_LC2_A18 = _LC2_A18~NOT;
_LC2_A18~NOT = LCELL( _EQ047);
  _EQ047 =  inte4 & !_LC1_A22
         #  inte3 & !_LC1_A22
         # !inte5 & !_LC1_A22;

-- Node name is '~1742~2' 
-- Equation name is '~1742~2', location is LC3_A18, type is buried.
-- synthesized logic cell 
_LC3_A18 = LCELL( _EQ048);
  _EQ048 = !inte3 & !_LC2_A18
         # !inte1 & !_LC2_A18
         #  _LC1_A21 & !_LC2_A18;

-- Node name is ':1760' 
-- Equation name is '_LC7_A19', type is buried 
_LC7_A19 = LCELL( _EQ049);
  _EQ049 =  inte5
         # !_LC1_A19 &  _LC2_A19;



Project Information                                  d:\vhdl3\count60_show.rpt

** COMPILATION SETTINGS & TIMES **

Processing Menu Commands
------------------------

Design Doctor                             = off

Logic Synthesis:

   Synthesis Type Used                    = Multi-Level

   Default Synthesis Style                = NORMAL

      Logic option settings in 'NORMAL' style for 'ACEX1K' family

      CARRY_CHAIN                         = ignore
      CARRY_CHAIN_LENGTH                  = 32
      CASCADE_CHAIN                       = ignore
      CASCADE_CHAIN_LENGTH                = 2
      DECOMPOSE_GATES                     = on
      DUPLICATE_LOGIC_EXTRACTION          = on
      MINIMIZATION                        = full
      MULTI_LEVEL_FACTORING               = on
      NOT_GATE_PUSH_BACK                  = on
      REDUCE_LOGIC                        = on
      REFACTORIZATION                     = on
      REGISTER_OPTIMIZATION               = on
      RESYNTHESIZE_NETWORK                = on
      SLOW_SLEW_RATE                      = off
      SUBFACTOR_EXTRACTION                = on
      IGNORE_SOFT_BUFFERS                 = on
      USE_LPM_FOR_AHDL_OPERATORS          = off

   Other logic synthesis settings:

      Automatic Global Clock              = on
      Automatic Global Clear              = on
      Automatic Global Preset             = on
      Automatic Global Output Enable      = on
      Automatic Fast I/O                  = off
      Automatic Register Packing          = off
      Automatic Open-Drain Pins           = on
      Automatic Implement in EAB          = off
      Optimize                            = 5

Default Timing Specifications: None

Cut All Bidir Feedback Timing Paths       = on
Cut All Clear & Preset Timing Paths       = on

Ignore Timing Assignments                 = off

Functional SNF Extractor                  = off

Linked SNF Extractor                      = off
Timing SNF Extractor                      = on
Optimize Timing SNF                       = off
Generate AHDL TDO File                    = off
Fitter Settings                           = NORMAL
Use Quartus Fitter                        = on
Smart Recompile                           = off
Total Recompile                           = off

Interfaces Menu Commands
------------------------

EDIF Netlist Writer                       = off
Verilog Netlist Writer                    = off
VHDL Netlist Writer                       = off

Compilation Times
-----------------

   Compiler Netlist Extractor             00:00:00
   Database Builder                       00:00:00
   Logic Synthesizer                      00:00:00
   Partitioner                            00:00:00
   Fitter                                 00:00:01
   Timing SNF Extractor                   00:00:00
   Assembler                              00:00:00
   --------------------------             --------
   Total Time                             00:00:01


Memory Allocated
-----------------

Peak memory allocated during compilation  = 20,673K