main.vhd

出租车计费系统的 实现

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity main is
   port (  clk1 :in  std_logic;
           key4 :in std_logic_vector(3 downto 0);
           minute,hour,day,month :out std_logic_vector(5 downto 0)
                    );
end;

architecture behv of main is
 
 signal set,add,start,arrive : std_logic;
 signal set_hour,set_minute,set_day,set_month :std_logic;
 signal second_clk,minute_clk,hour_clk,day_clk,month_clk :std_logic;
 signal adda,add2,add3,add4 : std_logic; 
 signal qq :std_logic_vector(2 downto 0);
signal result1,result2,result3,result4:std_logic_vector(5 downto 0);


  begin

process(key4,clk1)
 variable cnt8:std_logic_vector(7 downto 0);

 begin 


  if clk1'event and clk1='1' then
      case key4 is
  when "0001"=>set<='1';
  when "0010"=>adda<='1';add2<='1';add3<='1';add4<='1';
  when "0100"=>start<='1';
  when "1000"=>arrive<='1'; 
  when others=>set<='0';adda<='0';start<='0';arrive<='0';add2<='0';add3<='0';add4<='0';
 end case;
   if cnt8="00000000" then cnt8:="00000001"; second_clk<='1';
        else cnt8:=cnt8-1;  second_clk<='0';
      end if;

  end if;
end process;
process(set)

begin

if set'event and set ='1' then qq<=qq+1;
case qq is
when "001"=>set_minute<='1';
when "010"=>set_hour<='1';
when "011"=>set_day<='1';
when "100"=>set_month<='1';
when "101"=>qq<="000";
when others=>qq<="000";
end case;
end if;
end process;

process(second_clk)
variable cnt0:std_logic_vector(5 downto 0);
  begin
 if second_clk'event and second_clk ='1' then
    if cnt0="000000"  then cnt0:="111100";minute_clk<='1';
    else cnt0:=cnt0-1; minute_clk<='0';
    end if;
 end if;
end process;
     
process(adda)
variable cnt1 :  std_logic_vector(5 downto 0);

begin
 if adda'event and adda='1' then
     cnt1:=cnt1+1;
     end if;
result1<=cnt1;
end process;

process(minute_clk,result1)
variable scnt1 :std_logic_vector(5 downto 0);
  begin
  if minute_clk'event and minute_clk ='1'
     then scnt1:=result1;
          if scnt1="000000"  then scnt1:="111100";hour_clk<='1'; 
          else scnt1:=scnt1-1; hour_clk<='0';
          end if;
     end if;

minute<=scnt1;

end process;

process(hour_clk,add2,set_hour)
variable cnt2:std_logic_vector(5 downto 0);
begin
if set_hour='0' then cnt2:="000000";
  elsif add2'event and add2='1' then
     cnt2:=cnt2+1;
       if hour_clk'event and hour_clk ='1'
     then
          if cnt2="000000"  then cnt2:="011000";day_clk<='1'; 
          else cnt2:=cnt2-1; day_clk<='0';
          end if;

     hour<=cnt2;
     end if;
end if;

end process;

process(day_clk,add3,set_day)
variable cnt3:std_logic_vector(5 downto 0);
begin
if set_day='1' 
  then if add3'event and add3='1' then
     cnt3:=cnt3+1;
     end if;
  else if day_clk'event and day_clk ='1'
     then
          if cnt3="000000"  then cnt3:="011000";month_clk<='1'; 
          else cnt3:=cnt3-1; month_clk<='0';
          end if;

     day<=cnt3;
     end if;
end if;

end process;


process(month_clk,add4,set_month)
variable cnt4:std_logic_vector(5 downto 0);
begin
if set_month='1' 
  then if add4'event and add4='1' then
     cnt4:=cnt4+1;
     end if;
  else if month_clk'event and month_clk ='1'
     then
          if cnt4="000000"  then cnt4:="011000";
          else cnt4:=cnt4-1;
          end if;

     month<=cnt4;
     end if;
end if;

end process;


end ;