jiance.vhd

出租车计费系统的 实现

Library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
USE IEEE.STD_LOGIC_ARITH.ALL;
entity JIANCE is
port (
         CLKS,CLK:in std_logic;
         -- OUTY :OUT INTEGER RANGE 9 DOWNTO 0;
         --RESET,CNT_EN,LOAD1: OUT STD_LOGIC;
          COUT: OUT  STD_LOGIC);
end;
architecture behv of JIANCE is
  SIGNAL DIVCLK,EN,LOAD,RES,COT: STD_LOGIC;
  SIGNAL DIN:INTEGER RANGE 9 DOWNTO 0;
   BEGIN
     PROCESS(CLK)
     BEGIN
      IF CLK'EVENT AND CLK='1'  THEN DIVCLK<=NOT DIVCLK;
       END IF;  
   END PROCESS;
  PROCESS(CLK,DIVCLK)
  BEGIN
    IF DIVCLK='0' AND CLK='0'
       THEN RES<='1';
       ELSE RES<='0';
    END IF;

 END PROCESS;
PROCESS(DIVCLK,RES)
BEGIN
LOAD<=NOT DIVCLK; EN<=DIVCLK;
--LOAD1<=LOAD;CNT_EN<=EN;RESET<=RES;

END PROCESS;
process(CLKS,RES,EN)
 VARIABLE QQ:INTEGER RANGE 9 DOWNTO 0;
  BEGIN
     IF RES='1' THEN QQ:=0;COT<='0';
      ELSIF CLKS'EVENT AND CLKS='1' THEN
        IF EN='1' THEN
        IF QQ<9 THEN QQ:=QQ+1;
             ELSE QQ:=0;COT<='1';

       END IF;
       END IF;
         END IF;

          DIN<=QQ;
 END PROCESS;

PROCESS(LOAD,DIN,COT)
BEGIN
IF (LOAD'EVENT AND LOAD ='1')  then
      
  IF Din<4 AND COT='0'   THEN COUT<='1'; ELSE COUT<='0';
END IF;
END IF;
--OUTY<=DOUT;
end process;


END ;