📄 jfq3.vhd
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Library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
USE IEEE.STD_LOGIC_ARITH.ALL;
entity JFQ3 is
port (
CLK3,RESET,CON:in std_logic;
COF :OUT STD_LOGIC;
MONEY4:OUT INTEGER RANGE 9 DOWNTO 0 );
end;
architecture behv of JFQ3 is
SIGNAL CO: STD_LOGIC;
BEGIN
PROCESS(CLK3,CON)
VARIABLE CNT:INTEGER RANGE 9 DOWNTO 0;
BEGIN
IF RESET ='1' THEN CNT:=0;
ELSIF CLK3'EVENT AND CLK3='1' THEN
IF CON='1'
THEN
CNT:=CNT+1;
IF CNT>1
THEN CO<='1';
ELSE CO<='0';
END IF;
END IF;
END IF;
MONEY4<=CNT;
COF<=CO;
END PROCESS;
END ;
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