📄 jfq2.vhd
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Library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
USE IEEE.STD_LOGIC_ARITH.ALL;
entity JFQ2 is
port (
CLK2,RESET,CON:in std_logic;
COUT2 :OUT STD_LOGIC;
MONEY3:OUT INTEGER RANGE 9 DOWNTO 0 );
end;
architecture behv of JFQ2 is
SIGNAL CO2 : STD_LOGIC;
BEGIN
PROCESS(CLK2,CON)
VARIABLE CNT:INTEGER RANGE 9 DOWNTO 0;
BEGIN
IF RESET ='1' THEN CNT:=5;
ELSIF CLK2'EVENT AND CLK2='1' THEN
IF CON='1'
THEN
CNT:=CNT+1;
IF CNT>9
THEN CO2<='1';
CNT:=CNT-10;
ELSE CO2<='0';
END IF;
END IF;
END IF;
MONEY3<=CNT;
COUT2<=CO2;
END PROCESS;
END ;
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