yima.vhd

出租车计费系统的 实现

library ieee;
use ieee.std_logic_1164.all;
entity yima is
     port ( time_3,time_2,time_1,time_0:in integer range 9 downto 0;
            money_3,money_2,money_1,money_0:in integer range 9 downto 0;
            clk:in std_logic;
            data_out:out integer range 9 downto 0;
                       selout     :out integer range 0 to 7);
end entity ;
architecture one of yima is
signal data_in : integer range 9 downto 0;
signal sel : integer range 0 to 7;

begin
     process(clk)
     begin
          if clk'event and clk='1' 
             then sel <= sel+1;
          end if;
     end process;
     process(time_3,time_2,time_1,time_0,sel,money_3,money_2,money_1,money_0)
     begin
          case sel is
            when 0 => data_in <=time_0;
            when 1 => data_in <=time_1;
            when 2 => data_in <=time_2;
            when 3 => data_in <=time_3;
            when 4 => data_in <=money_0;
            when 5 => data_in <=money_1;
            when 6 => data_in <=money_2; 
            when 7 => data_in <=money_3;
            when others => NULL;
          end case;
               selout<=sel;
     data_out<=data_in;
     end process;

     end architecture one;