📄 km.vhd
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Library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
USE IEEE.STD_LOGIC_ARITH.ALL;
entity KM is
port (
CLK,RESET,CON:in std_logic;
COUT:OUT STD_LOGIC
);
end;
architecture behv of KM is
SIGNAL CO1: STD_LOGIC;
BEGIN
PROCESS(CLK,CON,RESET)
VARIABLE CNT:INTEGER RANGE 9 DOWNTO 0;
BEGIN
IF RESET ='1' THEN CNT:=0;CO1<='0';
ELSIF CLK'EVENT AND CLK='1' THEN
IF CON='1'
THEN
CNT:=CNT+1;
IF CNT>9
THEN CO1<='1';
END IF;
END IF;
END IF;
COUT<=CO1;
END PROCESS;
END ;
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