📄 jfq1.vhd
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library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
USE IEEE.STD_LOGIC_ARITH.ALL;
entity JFQ1 is
port (
CLKS,CLK,COF,CON,RESET,KM,JIANCE:in std_logic;
COUT1 :OUT STD_LOGIC;
MONEY1,MONEY2:OUT INTEGER RANGE 9 DOWNTO 0 );
end;
architecture behv of JFQ1 is
SIGNAL CO1,CO2,CLKO: STD_LOGIC;
BEGIN
PROCESS(CLK,CLKS,JIANCE)
BEGIN
IF JIANCE='1' THEN CLKO<=CLK;
ELSE CLKO<=CLKS;
END IF;
END PROCESS;
PROCESS(CLKO,COF,CON,JIANCE)
VARIABLE CNT1,CNT2:INTEGER RANGE 9 DOWNTO 0;
BEGIN
IF RESET='1' THEN CNT1:=0;CNT2:=0;
ELSIF CLKO'EVENT AND CLKO='1' THEN
IF CON='1' AND KM='1'
THEN
IF JIANCE='0' THEN
IF COF='0' THEN
CNT1:=CNT1+4;
IF CNT1>9 THEN
CNT1:=CNT1-10;
CNT2:=CNT2+2;
ELSE CNT2:=CNT2+1;
END IF;
ELSE
CNT1:=CNT1+1;
IF CNT1>9 THEN
CNT1:=CNT1-10;
CNT2:=CNT2+3;
ELSE CNT2:=CNT2+2;
END IF;
END IF;
ELSE
CNT2:=CNT2+4;
END IF;
IF CNT2>9
THEN CO1<='1';
CNT2:=CNT2-10;
ELSE CO1<='0';
END IF;
END IF;
END IF;
MONEY1<=CNT1;
MONEY2<=CNT2;
COUT1<=CO1;
END PROCESS;
END ;
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