biyesheji.map.rpt

基于logmap算法的vhdl的实现。 通信系统的log—map算法数字vhdl的实现

    Info: Found entity 1: ADD9
Info: Found 2 design units, including 1 entities, in source file E:/biyesheji/add.vhd
    Info: Found design unit 1: ADD-SCHARCH
    Info: Found entity 1: ADD
Info: Found 1 design units, including 1 entities, in source file E:/biyesheji/chip2.gdf
    Info: Found entity 1: chip2
Info: Found 2 design units, including 1 entities, in source file E:/biyesheji/compare.vhd
    Info: Found design unit 1: COMPARE-BEHV
    Info: Found entity 1: COMPARE
Info: Found 2 design units, including 1 entities, in source file E:/biyesheji/control.vhd
    Info: Found design unit 1: CONTROL-BEHV
    Info: Found entity 1: CONTROL
Info: Found 2 design units, including 1 entities, in source file E:/biyesheji/fenxin1.vhd
    Info: Found design unit 1: FENXIN1-HDLARCH
    Info: Found entity 1: FENXIN1
Info: Found 2 design units, including 1 entities, in source file E:/biyesheji/fenxin2.vhd
    Info: Found design unit 1: FENXIN2-HDLARCH
    Info: Found entity 1: FENXIN2
Info: Found 2 design units, including 1 entities, in source file E:/biyesheji/fifo3.vhd
    Info: Found design unit 1: fifo3-SYN
    Info: Found entity 1: fifo3
Error (10500): VHDL syntax error at fifo3_inst.vhd(1) near text "fifo3_inst";  expecting "entity", or "architecture", or "use", or "library", or "package", or "configuration" File: E:/biyesheji/fifo3_inst.vhd Line: 1
Info: Found 0 design units, including 0 entities, in source file E:/biyesheji/fifo3_inst.vhd
Info: Found 2 design units, including 1 entities, in source file E:/biyesheji/H_add.vhd
    Info: Found design unit 1: H_ADD-HDLARCH
    Info: Found entity 1: H_ADD
Info: Found 2 design units, including 1 entities, in source file E:/biyesheji/h_suber.vhd
    Info: Found design unit 1: H_SUBER-HDLARCH
    Info: Found entity 1: H_SUBER
Info: Found 2 design units, including 1 entities, in source file E:/biyesheji/jian8.vhd
    Info: Found design unit 1: JIAN8-HDLARCH
    Info: Found entity 1: JIAN8
Info: Found 2 design units, including 1 entities, in source file E:/biyesheji/ksubabs.vhd
    Info: Found design unit 1: ksubabs-HDLARCH
    Info: Found entity 1: ksubabs
Info: Found 1 design units, including 1 entities, in source file E:/biyesheji/lianxi.gdf
    Info: Found entity 1: lianxi
Error (10522): VHDL syntax error at lihui01.vhd(5): experienced unexpected end-of-file ;  expecting "entity", or "architecture", or "use", or "library", or "package", or "configuration" File: E:/biyesheji/lihui01.vhd Line: 5
Info: Found 0 design units, including 0 entities, in source file E:/biyesheji/lihui01.vhd
Info: Found 1 design units, including 1 entities, in source file E:/biyesheji/lihui02.gdf
    Info: Found entity 1: lihui02
Info: Found 2 design units, including 1 entities, in source file E:/biyesheji/log_map.vhd
    Info: Found design unit 1: LOG_MAP-BEHV
    Info: Found entity 1: LOG_MAP
Info: Found 2 design units, including 1 entities, in source file E:/biyesheji/log_map_chip2.vhd
    Info: Found design unit 1: LOG_MAP_CHIP2-BEHV
    Info: Found entity 1: LOG_MAP_CHIP2
Info: Found 2 design units, including 1 entities, in source file E:/biyesheji/log_map_chip.vhd
    Info: Found design unit 1: LOG_MAP_CHIP-BEHV
    Info: Found entity 1: LOG_MAP_CHIP
Info: Found 2 design units, including 1 entities, in source file E:/biyesheji/max.vhd
    Info: Found design unit 1: max-HDLARCH
    Info: Found entity 1: max
Info: Found 2 design units, including 1 entities, in source file E:/biyesheji/maxout.vhd
    Info: Found design unit 1: MAXOUT-HDLARCH
    Info: Found entity 1: MAXOUT
Info: Found 1 design units, including 1 entities, in source file E:/biyesheji/maxstar.gdf
    Info: Found entity 1: maxstar
Info: Found 2 design units, including 1 entities, in source file E:/biyesheji/maxstar_ch.vhd
    Info: Found design unit 1: MAXSTAR_CH-HDLARCH
    Info: Found entity 1: MAXSTAR_CH
Info: Found 2 design units, including 1 entities, in source file E:/biyesheji/maxstarnew.vhd
    Info: Found design unit 1: MAXSTARNEW-BEHV
    Info: Found entity 1: MAXSTARNEW
Info: Found 2 design units, including 1 entities, in source file E:/biyesheji/maxstartxt.vhd
    Info: Found design unit 1: MAXSTARTXT-BEHV
    Info: Found entity 1: MAXSTARTXT
Info: Found 2 design units, including 1 entities, in source file E:/biyesheji/newadd8.vhd
    Info: Found design unit 1: NEWADD8-HDLARCH
    Info: Found entity 1: NEWADD8
Error (10500): VHDL syntax error at newcompare.vhd(18) near text "IF";  expecting "end", or "(", or an identifier ("if" is a reserved keyword), or a parallel statement,  File: E:/biyesheji/newcompare.vhd Line: 18
Error (10500): VHDL syntax error at newcompare.vhd(18) near text "ELSE";  expecting "end", or "(", or an identifier ("else" is a reserved keyword), or a parallel statement,  File: E:/biyesheji/newcompare.vhd Line: 18
Error (10500): VHDL syntax error at newcompare.vhd(18) near text "IF";  expecting ";", or an identifier ("if" is a reserved keyword), or "architecture" File: E:/biyesheji/newcompare.vhd Line: 18
Error (10500): VHDL syntax error at newcompare.vhd(19) near text "ELSE";  expecting "end", or "(", or an identifier ("else" is a reserved keyword), or a parallel statement,  File: E:/biyesheji/newcompare.vhd Line: 19
Error (10500): VHDL syntax error at newcompare.vhd(19) near text "IF";  expecting ";", or an identifier ("if" is a reserved keyword), or "architecture" File: E:/biyesheji/newcompare.vhd Line: 19
Error (10500): VHDL syntax error at newcompare.vhd(20) near text "ELSE";  expecting "end", or "(", or an identifier ("else" is a reserved keyword), or a parallel statement,  File: E:/biyesheji/newcompare.vhd Line: 20
Error (10500): VHDL syntax error at newcompare.vhd(20) near text "IF";  expecting ";", or an identifier ("if" is a reserved keyword), or "architecture" File: E:/biyesheji/newcompare.vhd Line: 20
Error (10500): VHDL syntax error at newcompare.vhd(21) near text "ELSE";  expecting "end", or "(", or an identifier ("else" is a reserved keyword), or a parallel statement,  File: E:/biyesheji/newcompare.vhd Line: 21
Error (10500): VHDL syntax error at newcompare.vhd(21) near text "IF";  expecting ";", or an identifier ("if" is a reserved keyword), or "architecture" File: E:/biyesheji/newcompare.vhd Line: 21
Error (10500): VHDL syntax error at newcompare.vhd(22) near text "ELSE";  expecting "end", or "(", or an identifier ("else" is a reserved keyword), or a parallel statement,  File: E:/biyesheji/newcompare.vhd Line: 22
Error (10500): VHDL syntax error at newcompare.vhd(22) near text "IF";  expecting ";", or an identifier ("if" is a reserved keyword), or "architecture" File: E:/biyesheji/newcompare.vhd Line: 22
Error (10500): VHDL syntax error at newcompare.vhd(23) near text "ELSE";  expecting "end", or "(", or an identifier ("else" is a reserved keyword), or a parallel statement,  File: E:/biyesheji/newcompare.vhd Line: 23
Error (10500): VHDL syntax error at newcompare.vhd(23) near text "IF";  expecting ";", or an identifier ("if" is a reserved keyword), or "architecture" File: E:/biyesheji/newcompare.vhd Line: 23
Error (10500): VHDL syntax error at newcompare.vhd(24) near text "ELSE";  expecting "end", or "(", or an identifier ("else" is a reserved keyword), or a parallel statement,  File: E:/biyesheji/newcompare.vhd Line: 24
Error (10500): VHDL syntax error at newcompare.vhd(24) near text "IF";  expecting ";", or an identifier ("if" is a reserved keyword), or "architecture" File: E:/biyesheji/newcompare.vhd Line: 24
Info: Found 0 design units, including 0 entities, in source file E:/biyesheji/newcompare.vhd
Info: Found 2 design units, including 1 entities, in source file E:/biyesheji/ram_chip2.vhd
    Info: Found design unit 1: ram_chip2-SYN
    Info: Found entity 1: ram_chip2
Error (10500): VHDL syntax error at ram_chip2_inst.vhd(1) near text "ram_chip2_inst";  expecting "entity", or "architecture", or "use", or "library", or "package", or "configuration" File: E:/biyesheji/ram_chip2_inst.vhd Line: 1
Info: Found 0 design units, including 0 entities, in source file E:/biyesheji/ram_chip2_inst.vhd
Info: Found 0 design units, including 0 entities, in source file E:/biyesheji/rom_chip1.vhd
Critical Warning: Ignored duplicate design unit "MAXSTAR_CH-HDLARCH" in file E:/biyesheji/maxstar_ch.vhd
Error: Entity "MAXSTAR_CH" in file E:/biyesheji/maxstar_ch.vhd already exists in file E:/biyesheji/shixian2.vhd File: E:/biyesheji/maxstar_ch.vhd Line: 4
Info: Found 2 design units, including 1 entities, in source file E:/biyesheji/shixian2.vhd
    Info: Found design unit 1: MAXSTAR_CH-HDLARCH
Info: Found 2 design units, including 1 entities, in source file E:/biyesheji/shixian3.vhd
    Info: Found design unit 1: SHIXIAN3-HDLARCH
    Info: Found entity 1: SHIXIAN3
Info: Found 1 design units, including 1 entities, in source file E:/biyesheji/shiyan1.gdf
    Info: Found entity 1: shiyan1
Info: Found 2 design units, including 1 entities, in source file E:/biyesheji/sub8.vhd
    Info: Found design unit 1: SUB8-HDLARCH
    Info: Found entity 1: SUB8
Info: Found 2 design units, including 1 entities, in source file E:/biyesheji/suber.vhd
    Info: Found design unit 1: SUBER-SCHARCH
    Info: Found entity 1: SUBER
Info: Found 1 design units, including 1 entities, in source file E:/biyesheji/yuanjian1.gdf
    Info: Found entity 1: yuanjian1
Info: Found 2 design units, including 1 entities, in source file E:/biyesheji/yuanzheng.vhd
    Info: Found design unit 1: YUANZHENG-BEHV
    Info: Found entity 1: YUANZHENG
Info: Found 2 design units, including 1 entities, in source file E:/biyesheji/absxy.vhd
    Info: Found design unit 1: ABSXY-HDLARCH
    Info: Found entity 1: ABSXY
Error (10522): VHDL syntax error at add1.vhd(6): experienced unexpected end-of-file ;  expecting "entity", or "architecture", or "use", or "library", or "package", or "configuration" File: E:/biyesheji/add1.vhd Line: 6
Info: Found 0 design units, including 0 entities, in source file E:/biyesheji/add1.vhd
Info: Found 2 design units, including 1 entities, in source file E:/biyesheji/add4b.vhd
    Info: Found design unit 1: add4b-one
    Info: Found entity 1: add4b
Info: Found 2 design units, including 1 entities, in source file E:/biyesheji/add8.Vhd
    Info: Found design unit 1: ADD8-HDLARCH
    Info: Found entity 1: ADD8
Critical Warning: Ignored duplicate design unit "ADD8B-HDLARCH" in file E:/biyesheji/add8b.vhd
Error: Entity "ADD8B" in file E:/biyesheji/add8b.vhd already exists in file ADD8B.vhd File: E:/biyesheji/add8b.vhd Line: 3
Info: Found 2 design units, including 1 entities, in source file ADD8B.vhd
    Info: Found design unit 1: ADD8B-HDLARCH
Error: Quartus II Analysis & Synthesis was unsuccessful. 21 errors, 2 warnings
    Error: Processing ended: Sun Mar 26 00:17:22 2006
    Error: Elapsed time: 00:00:08